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9-2-3. Signal description
Signal name
IN/OUT
Function
CLK14M
IN
A 14.31818MHz clock input used lor the CPU clock and also used lor the timer clock after dividing it to
1/12.
CLK24M
IN
A 23.9616MHz clock input used for the CPU clock and also used for the 82C50A UART clock after divid-
ing it to 1/13.
SYSCLK
OUT
110, slot strob,e signal. A 1/2 CLK14M or 1/4 CLK24M is delivered.
PRCLK
OUT
CP'U clock. A CLK14M or CLK24M input or 1/2 CLK24M is delivered with the clock selection.
SI-0
IN
Bus cycle- status signal input from the CPU.
MIO
OUT
MamQ[)LancWLQselectJrom-tos-cf'U.
ALE
out
Strobe to externally latch the CPU output address.
MEMR
IN/OUT
~emory
read signaL During
tne
memory
re:actcyCle
and refresh eyere, a low state of strobe signal is is-
. sued,
except,wh~ri
reading the memory signal on the local bus.
MEMW
IN/OUT
ME!,mory write signaL Except for th,? memory write of the local bus, a low state of strobe signal is issued
during the memory write cycle.
lOR
IN/OUT
,
1/0 J89d
§ignal.
A
low state of strobe, is issued during the 110 read cycle.
lOW
IN/OUT
110 wr'!te s,ignal. A low state of strobe is
is~ued during the 110 write cycle.
LMSEL
OUT
Indicates accessing of address below 1 MB which is ,used to generate SMEMR or SMEMW in the exter-
nal circuit.
,
EALE
OUT
Address latch signal,used by the expansion unit employed to emulate a 6MHz bus cycle.
PWRGOOD
IN
Input from the power supply unit to indicate that the -supply voltage is normal.
RESCPU
OUT
Reset signal
[§~l,.Ied
When returning from the protect mode to the real mode, or when exiting from the
shut down-,cycle. Connected only to the CPU.
BRESET
OUT
Sy~tem rese{signal.
READY
OUT
Signal'used to inform the CPU the end of the cycle currently executed.
OWS
IN
Signal used to request the system to terminate the bus cycle currently executed by the device on the
I/O slot.
10CHRDY
IN
Signal used to request the system to extend the bus cycle currently executed by the device on the I/O
slot.
HOLD
OUT
Signal used to request the CPU to hand down the bus.
HLDA
IN
Acknowledge to the CPU for its hold request:
HREO
IN
Bus request signal from the DMAC.
HLDAK
OUT
Acknowledge request to the DMAC.
AEN
OUT
Signal used to indicate that it is a DMA cycle not by the master. A high on this line indicate the DMA
cycle.
MA21-14
OUT
Pseudo-SRAM high address. For MA21-19, the address from the CPU is internally latched for output.
PCSLO
Pseudo-SRAM chip select. Four chip selects are used to access 16 bits of 2-bank pseudo-SRAM.
PCSHO
OUT
BankO
Bankl
PCSLt
Low byte
PCSLO
PCSLt
PCSHI
High bYte
PCSHO
PCSHI
PSOE
OUT
Pseudo-SRAM output enable signal.
PSWE
OUT
Pseudo-SRAM write enable signal.
REFR
OUT
Pseudo-SRAM refresh signal.
CSBIOS
OUT
Display BIOS chip select signal.
NMI
OUT
Non-maskable interrupt signal to the CPU.
10CHCKN
IN
Signal used to inform an error in I/O slot.
PCKN
IN
Parity check error signal.
INTR
OUT
Interrupt request signal to the CPU.
IROI
Interrupt request signal from an external device.
IR03-7
IR08N
IN
IR09-12
IR014-15
LA23-0
IN/OUT
CPU side address signal.
SA9-0
IN/OUT
System side address signal.
BHE
IN/OUT
Data bus access signal, high side.
SBHE
IN/OUT
Latched data bus access signal, high side.
D7-0
IN/OUT
CPU side data bus, low side.
D15-8
IN/OUT
CPU/system side data bus, high side.
XD7-0
IN/OUT
System side data bus, low side.
Table 9-2 (a)
_____________________________________ 54 ________________________________ __
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