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SIGNAL DESCRIPTIONS
The block diagram in Figure 1, shows the pin connection with the
major internal functions of the MC146818 Real-Time Clock plus RAM.
The following paragraphs describe the function of each pin.
Voo, VSS
DC
power is
provided to the part on these two pins, Vao being the
more positive voltage. The minimum and maximum voltages are
listed in the Electrical Characteristics tables.
.. OSC1,
OSC2~
TIME BASE, INPUTS·
The time base for the time functions may be an external signal or the
crystal oscillator. External square waves at 4.194304 MHz, 1.048576
MHz,
or
32.768 kHz may be connected to
aSCi.
The internal time-
base frequency to be used is chosen in Register A.
The on-chip oscillator is designed for a parallel resonant.
AT cut crystal at 4,194304 MHz or 1 ,048576 MHz frequencies,
CKOUT-CLOCK OUT, OUTPUT
The CKOUT pin is an Dutput at the time-base frequency divided by 1
Of
4. A major use for CKOUT is as the input clock to the microproces-
sor; thereby saving the cost of a second crystal. The frequency of
CKOUT depends upon the time-base frequency and the state of the
CKFS
pin as
shown in Table 9-3.
CKFS-CLOCK OUT FREQUENCY SELECT, INPUT
When the CKFS pin is tied to Voo
it
causes CKOUT to be the same
frequency as the time base at the
aSCi
pin. When CKFS is tied to
Vss, CKOUT is the
aSCi
time-base frequency divided
by
four. Table
2
summarizes
the effect of CKFS.
lime Base (OSC1)
Clock Frequency
Clock Frequency
Frequency
Select Pin (CKFS)
Output Pin (CKOUT)
4,194304 MHz
High
4,194304 MHz
4.194304 MHz
Low
1,048576 MHz
1,048576 MHz
High
1.048576 MHz
1,048576 MHz
Low
262,144 kHz
32.768 kHz
High
32,768 kHz
32,768 kHz
Low
8,192 kHz
Table 9-3. Clock output frequencies
SQW-SQUARE WAVE, OUTPUT
The
saw
pin can output a signal from one of the 15 taps provided
by
the 22 internal-divider stages. The frequency of the
saw
may be
altered by programming Register A. The SOW signal may be turned
on and off using the SQWE bit in Register B.
-65-
-
P C-6220
ADO-AD7-MULTIPLEXED BIDIRECTIONAL
ADDRESS/DATA BUS
Multiplexed bus processors
save
pins by presenting the address
during the first portion of the bus cycle and using the same pins
during the second portion for data. Address-then-data multiplexing
does not slow the access time of the MC146818 since the bus
rever-
sal from address to data is occurring during the internal RAM access
time.
The address must be valid just prior to the fall of ASIALE at which
time the MC146818 latches the address from ADO to AD5. Valid write
data must be presented and held stable during the latter portion oL
the OS or WR pulses. In a read cycle, the MC146818 outputs eight
bits of data during the latter portion of the DS or RD pulses, then
ceases driving the bus (returns the output drivers to the high-im-
pedance state) when OS falls in the Motorola case of MOTEL or RD
rises in the other case.
AS-MULTIPLEXED ADDRESS STROBE, INPUT
A positive gOing multiplexed address strobe pulse selVes to demul-
tiplex the bus. The falling edge of AS or ALE causes the address to
be latched within the MC146818. The automatic MOTEL circuit in the
MC146818. The automatic MOTEL circuit in the MC146818 also
latches the state of the DS pin with the falling edge of AS or ALE.
OS-DATA STROBE OR READ, INPUT
The OS pin has two interpretations via the MOTEL circuit. When
emanating from a Motorola type processor, OS is a positive pulse
during the latter portion of the bus cycle, and is variously called OS
(data strobe), E (enable), and £12 (£12 clock). During read cycles, OS
signifies the time that the RTC is to drive the bidirectional bus. In write
cycles, the trailing edge of OS causes the Real-Time Clock plus RAM
to latch the written data.
The second MOTEL interpretation of OS is that of RD, MEMR, or
IIOR emanating from the competitor type processor. In this case, DS
identifies the time period when the real-time clock plus RAM drives
the bus with read data. This interpretation of OS is also the same as
an output-enable signal on a typical memory.
The MOTEL circuit, within the MC146818, latches the state of the OS
pin on the falling edge of AS/ALE. When the Motorola mode of
MOTEL is desired OS must be low during ASIALE, which is the case
with the Motorola multiplexed bus processors. To ensure the com-
petitor mode of MOTEL, the DS pin must remain high during the time
AS/ALE is high,
R/W-READ/WRITE, INPUT
The MOTEL circuit treats the Rm pin in one of two ways. When a
Motorola type processor is connected, Rm is a level which indicates
whether the current cycle is a read or write. A read cycle is indicated
with a high level on RiW while OS is high, whereas a write cycle is a
Iowan RtW during OS.
The second interpretation of RiW is as a negative write pulse, WA,
MEMW, and i/OW from competitor type processors. The MOTEL cir-
cuit in this mode gives
Riw
pin the same meaning as the write
(W)
pulse on many generic RAMs.
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