Advertisement
-
=llGJ=6:l2~~--
The:PWRTIM register_js used to' pi'ogram;the_ tinie for, , auto. power
save that it may be set in increment of one minute ih
a.
range. of 0 to
~ 5-_minutes.~
However, the actual time is
,~horter
than the programmed
time within a minute. When PST3-0 "a.re:all "-1", the- settil)g, wiJl.-be
14-1,5:minutes. ,It is, possibls_ to read/write and Hie' set vallie is read. It
is allocated: to 09H of the 8h'arp origi'nar port whose bit definitIon is
given next.
-
PWRTIM registe'
Bit
Signal name
Significan'f':e
When reset, ARTS-D are all set to "1
n
and the bit 7 is 'reset Siinilar as
the auto_power saye
1
,an interrupt
requ~t
from the 8042_ (IRQ) turns
hign
b~f()rethe ~rog[am~ed:tirne,
the
set
value is loaded In the timer
and the count starts aU over again from the beginninQ. The_timer"will
be 'reloaded wh'en "the" PWRCONT register, ATSTBY register; or
RS'MTIMr~gister 01 the Sharp original port is written,
' ..
,
In either case 01 (1) and (2), occurrence of NMI does the same
process and requires software support. The following ,are
r~quired
in
toe NMj' routine in'order to power down during the resume m~de.
,
' "
'
' "
,
(1) Judges the NMI cause,
Q-3
PST!l:-3
4-7,
RESERVED
Auto power save time setting
.
'Reserved.
R~adlwrite
possible.
-
---(2)-AIFWcrrggisters-ott_iCelVCC supply) Installed to the system
mustbe saved;to the expanded.CMOS RAM,
When reset. PST3'-O are set 10 '''1'' and-others are reset.
When IRQ1 which is the interrupt request from the 8024 goes high
before the set time, the set valtie is reloaded in the tiiner and starts to
count from the sfarfall over again.' The timer will be reloaded even if
the PWRCNT register,ATSTBY register or PWRTIM register 01 the
~ha~p ~.ori~inal
port is __
'!iritt~n.
'
4.8.~.
RE!$urnE! functiqn (not ulled for thePC-6;!20)
1h:us~'the~-re,s'ume_ fu~ction~,
it,
has "to"be enabled ,by:
writi~g'''1''
_in
RsMEN 01 the' RSMCNTregister, Th. RSMCNT tegister is' an 8-bit
read/Write register which is allocated: to'
aSH
of the Sharp original port
who~e_
biJ definiti9n is
giv~n
n,ext.
RSMCNT register
.
Bit
Signal name
Significance
0
RSMEN
' Resume mode setting
1
CIEN
Reserved. Read/write possible.
2
MRIEN
,
Reserved. Read/write possible.
3~7
RESERVED
Rese.rve,d .. ,
~~ad!writ~
possible.
When reset, all-are reset to
"0".
In the resume_ mode (RSMEN=1), there are two cases that moves to
the power down state by shutting the power supply
(Vee) off with the
memory backed up.
(1) Input of a loW to high transHion signal from the RSMS line.
(2) No key operation is done within the prescribed time.
In the case of (1); a high state 01 signal is issued from the NMIline at
a low to high' transition of the signal input from the RSMSW line to
apply NMI to the CPU. On the other hand, in the case 01 (2), the
resume controller internal timer coritinues to count while there is no
interrupt request from the 8042. Woen the programm'ed
time
is
reached, the NMI is caused . .But simil'ar as the sleep function, a low
on the EXPND input prohibit the NMI and the resume function does
not take place. The state of the EXPND input can be' 'scanned on
EXPND olthe EXSTAT register.
When using the resume function by"the timer (auto resurTie), the timer
must be turned on after writing "1" to ASVCC 01 the ATSTBY register
and the time that the power down is expected" must be set in the
RSMTIM register. It would be possible to program it in increments of
one minute within a range of 0 to 127 minutes. actual time is shorter
than the programmed time within a minute. When ARTS-O are all,"1",
the ~etVrlg, ~111. _f;1:e.J~6~127"mi9,u~~,~~ ,'t ,is 'posslb!~ t9 read/write, and'
the set value is read. It is allocated to OAH of the Sharp original port
whose bit definition is given next.
PWRTIM register
Bit
-Sign'al name
Significance
0-6
ARTO-6
Auto resume mode setting
7
RESERVED
Reserved. Readlwrite possible.
·5ff·
(3) If the VRAM contents maynofbe:reiained, -ifhas:tb
be'saveel
in
the
pseOdo~SRAM'private
area (256KB),
(4) All CPU registers at NMloccurrence must be saved to the stack
and SS:SP must be written in the CMOS RAM.
(5) In' order to shut down- the 'system poWer 'supply, "0'"
,m,ust'
be
Y1ritl~n 'ih
peVeC
'ohhe 'PWRCNT'r~gister,
"
,
To
judge
th~~aus~
01 NMI at
(1),
RSMNMI of the I'JMIFCT register
must be' scanned:' If ';1", an NMi occurrence 'is i'ndicated, by the
RSMSW input or the resume timer. The NMIFCT register
Is' a
read
oniy register which Is-used to jUdge the NMi caus-e which is allocated
to OFH-ofthe ,Sharp original-port whose bit definhion is shown next.
NMIFCT register
Bit
Sig~al
name
Significance,
0
RSMNMI
On state of the resume NMI request
1-7
-
Undefined. Re<:!ds "0" at all times.
To restore from the_ power down state in the resume-mode, the sys-
tem power must be turned on and PWRGOOD input must change
from low to 'high. Because a reset is' applied in this instance, the
following process takes place in the initialization routine after the
reset.
(1) Reset cause is judged.
(2) The contents 01
1/0
registers saved in the CMOS RAM and are
loaded to devices.
.
(3) The contents of the VRAM are loaded from the private'area of the
pseudo .. SRAM (in case the contents of the VRAM may not be
retained).
(4) SS:SP is read Irom
the
CMOS RAM' and all CPU registers are
restored from the stack.
To judge the reset cause in (1), RCR 01 the RSTFCT register is
scanned. If "1 ", it indicates to turn off the
vce
supply by software in
order to power down if) 'the. resume
niode~
The RSTFCT registeir- is a
read only register used to judge the reset cause. When this register is
scanned, each bit 01 RCR, RCCI,and RCMRI is reset to
"0';.
It is
allocated to OCH of the Sharp' Original port whose bit definition is
shown next.
RSTFCF register
Bit
Signal name'
Significance
0
-
Undefined--: Reads "0" aralJ--times.
1
RCR
On stat" of the system poWer
(VCC)
off request
2
RCCI
state of the power on cause by the CI
input of the internal SIO.
3
RCMRI
State of the power on'ca:use
by
the RI
input of the internal modem.
4-7
-
Undefined. Reads "0" at all times.
RCCI and RCMRI 01 the RSTFCT register is used to support the auto
sensor from the internal SIO and the internal modem.
Advertisement
Chapters
