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. -__
~~--62:Itb.-_
4.11. Serial interface
.-:
,-:",.,,-
The 82C50- UART is internally,contairied- in" this chip' as a serial ,inter-
face and sup'ports ,a' single channel
RS~232C
interface· using th'e ax-
te-nia/ 'RS-232C.
ariver·
as
an.
internal SIO. This also 'used for the
interface
with
the internal modem.
Two seria.l
l
interfaces
may
be port allocated and set:on'or off, which
thee SIOCFRregister is used for the RS·232C
~nd:
the MDMCFR
register fat· the internal' modem;
The
SIOCFR register. is a
7~bit
"read/writs' register which, is _allocated to· 01 H of the Sharp original
port.-
The MDMCFR-register"ls a 2-bit re'ad/write register -which is allocated
to
03H
of the Sharp original port.
: ):'.
"
The table next shoW's, bit" definition.
SIOCFR-register:
-
Bit
Signa[name
Significance
.
0-2
'FDD0-2
; Rese'road.' Read/write possible. '
S
SW11*2
Internal'SIO'part allacation
4
>:SIOEN'
l~terha'f
810
onloff setting
5
:l:INTKEY'
-AeservecL -Read/write 'possible.
6
>:LCDEN
-Display deVice selection
7
-
Undefined. Reads
"on
at all times.
MDMCFR register
,
Bit
Signal name
I
SignificaAce
0
OUTSEL
MORSTNoutput signal selection
1-3
-
Undefined. Reads "0" at all times.
4
>:MDMEN' , Internal modem on/off setting
5-7
-
Vndefined. Reads "0" at all times. ,
When reset, >:SIOEN of the
sib
CFR register and >:MDMEN of the
MDMCFR register are set hili" aJid-a11 athers are reset.
>:SIOEN and S1011>:2 of the SIOCFR register may be revised of their
contents when written to. "02" to the Sharp ariginal port. The inverted
bit 4 of the 02H port corresponds to S1011>:2 and bit 5 to SIOEN.
The table below shows the, ports that allocated by the setting of
SIOCFFiand MDMCFR reilisters vs. active input to IRQ3 and IRQ4 of
the 82C59A.
'
>:SIOEN "'MDMEN SI01/>:2
Internal Internal
IRQ3
IRQ4
SIO
modem
input
input
a
0
0
COM2
COM1
Internal Internal
SIO
madem
0
0
1
COM1
COM2
Internal Internal
modem
SIO
0
1
0
COM2
OFF
Internal External
SIO
IRQ4
0
1
1
COM1
OFF
External Internal
IRQ3
SIO
1
0
0
OFF
COM1
External Internal
IRQ3
modem
1
0
1
OFF
COM2
Internal External
m0gem.
IRQ4
1
1
0
OFF
OFF
External External
IRQ3
IRQ4
1
1
1
OFF
OFF
External External
IRQ3
IRQ4
60
The
_RS~232C
inteiiace_serial input/output and;contro[' 'signals'can, be
inverted with POl:lNV, of the VGACNT register. Whet; POLlN)'( is.at
"1
n,
the pa!arity
iJi~erts.
The VGACNT. register is -allocated to .oEH_ of
the Sharp original p0it'who.se bit defhiitian is as sho.wn next '
VGACNT register
Bit
o
POLINV
RS·23ZC fnpuVputput polarity inversion
1
DISVGA' lil!ernal VGAbhloff setting
2,:3
PWFiDWN1,2
VGAcdnti611~rmbdesetting
'4 ...
7, .
RESERVED' 'Fi,eserved.ReadiWri\e, pdssible ••.. ,
To., reset the
int~rnal
modem (that can' be, insta'iled wIthin the
machine), the outputf[om the MORS'rN line Is used. The 1-blrblitput
of the MORSTN output pori can be switched with' the port select
signal output usirigOUTSEL of tfle MDMcFR tegister. When OUT-
SEL is-'at"1
n;-
the; bit 3 af the
1/0
address ,204H'p6ri: [S-is:~ued. When
"0"; the 'decode~ signai- of-the
1/0
ad?ress 202H is'issued as
ei
port
sel~ct
signal: The 202H port'is a 'read/write interhal_I/O-reglsterwhose
bit definitian is shown next.
202H port
c-',; -
,
. Bit
Sighai ~ame
. Significance
0-2
RESERVED
ReseNed. Readlwrite passible
3
MORSTN
Internal modem reset signal
4
RESERVED
Res9Ned_ Read/write possible
5-7
-
Undefined. Reads "0" at all times.
.
lijhsn 'reset, bits
0-4
i:lre
~eset.
4.12. RTC and CMOS RAM
Fdr this chip, RTe iscontroll,ed byAS; DS, R/W, and SCRTCN out-
puts. Por setup expansion, a2KB CMOS RAM is provided.
Among 11 bits address input of the 2KB CMOS RAM, the low 6 bits is
connected to the I/O 070H port bits 0-5, and high 5 bits to the latch
address bits 10-14. Which is to be selected, RTC or CMOS RAM,
when the 1/0 071 H port is accessed is determined by the data in the
I/O 70H bit
6.
When "0": RTC is selected and "1" the CMOS RAM.
See the figure belaw for the mapping af the RTC and the CMOS
RAM.
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