Advertisement
Read (Device
-t
Master)
16/8
LOC
BHE
AD
GA
GB
GC
16
L
D
a
1
1
a
1
a
1
1
a
a
1
1
1
1
I
a
a
a
a
a
1
a
a
1
a
a
1
a
a
a
ELS
Q
Q
Q
1
1
1
a
a
1
1
a
1
a
1
1
8
I
a
a
a
1
a
1
a
a
1
a
a
1
a
a
a
ElS
a
a
a
1
1
1
a
a
1
1
a
1
a
a
1
Table 4·6 (e)
4-2-2. Memory sub system
This unit is equipped with 1 MB RAM, 64KB system BIOS ROM, and
32KB display BIOS ROM as standard system memory.
The RAM is composed of eighl pseudo·slalic RAM's of 128KB x
8.Two optional 1 MB memory cards can be added to expand memory
to max. 3MB. Syslem BIOS and display BIOS are provided in Ihe
ROM (128KB x 16). The ROM is provided in a ROM board separate
from the main board and connected to the main board via 50-pin
connector. Fig. 4-5 shows the memory map.
Address
OFFFFFF
h
OFFOOOOh
0300000
h
0200000
h
0100000
OFOOODO
OC8000h
OCOOOOh
OAQOOOh
h
h
............... 3MB
System
BIOS
Extended
1MB
RAM area
System
BIOS
Wjndow-A
EMS/SLOT
".
area
Display BIOS
...... ....
Video RAM
Window·B
..
Conventional
. . . . . . . . . . . . . . . . . . . . . . . . . . . . : · · . . 9""·'
page-b
...............................
~
(1) ROM
-
P C-6220
ROM address signal is supplied by latching the CPU address at the
rising of the status signal by the peripheral control LSI (L295H22).
The reason why status signal instead of other signals is used for latch
is to decrease weight by supplying outputs to the ROM. The upper
side of data signal Is connected to the CPU data. For the lower side
of data, ROM access buffer is used to delay data transmission to
reduce the weight number. The chip select signal ("CSSIOS) of ROM
is generated by the SC9889A1B LSI.
Immediately after reset, the CPU makes access to the highest posi-
tion (OFFFFFOh) of address area. When JMPFAR command is ex-
ecuted, access is made near OOFFFFOh. At that time, the chip select
signal becomes low at OFFDOOOh - OFFFFFFh and OOFOOOOh -
OOFFFFFh 10 select the same ROM. Since Ihe display BIOS is in-
cluded in the same ROM, the chip enable signal becomes active in
Ihe display BIOS area OOCOOOOh - OOC7FFFh. The output enable
signal uses "MEMR signal. The data buffer enable signal in the lower
side for only ROM reading uses ROM chip select signal and "MEMR
signal. Fig. 4-6 shows ROM read timing.
PRCLK
'SO,'S1
A23-AO
"MEMR
"READY
...... 1
Note: Waveform shown in dotted line is for 12MHz operation.
Fig. 4-4
(2) RAM
(2)-1. Pseudo-SRAM control
This chip supports control of a maximum 4MB of the pseudo-SRAM.
Memory has three address spaces of the system area, EMS control
area, and private area. The EMS control area can further be divided
into three subsections of conventional area, extended area, and EMS
area
by
the internal
1/0
register setting.
(1)
Syslem area
The area of 256KB is allocated to OOOOOOH . . . . . 03FFFFH as the conven-
tional memory.
(2) EMS control area
Address can be allocated to three areas using the internal
1/0
register
setting,
(a) Convectional memory setting
An address space of 384KB can be allocated to 040000 -
09FFFFH
as a
conventional memory area.
(b) EXlended memory setting
Address space can be allocated after
10DaDOH
as an extended
memory area.
(c) EMS area
To support the EMS version 4.0, 34 windows of 16KB increments
can be mapped in D4DDDD-D9FFFH and DC8DDDH-DEFFFH .
(3)
Privale area
Using the internal I/O register setting, a 256KB of address space is
allocaled to DEDDDDH-DEFFFFH (accessed by bank select), which is
to be used to save the VRAM contents during the resume and used
by the system. The private area may be eliminated by the internal
1/0
~~._.j:=~=~
register setting.
............
~
..
~.~
..
~
..
~
..
~.~.
-=-_...
------NG:r-E-:- WUh-tfle---GUr-f-9nt-v-er-siGR-Of.-this-LSl--{.TS1 )rU-does.not..assur"e _ _ _ _
IEMS area
---04000011
Conventional
the interleave in the 12MHZ non-wait mode. Where, "0" must
area
be written to INTLV of the SPRAMCFL register discussed
later.
..
OOOOOOh
............................... .1..-_---'
Fig. 4·3
-21-
Advertisement
Chapters
