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Pin Description Tlible
,
" ,
,
,
,
Flatpack
--
.·Pin No.
Name
'
,
Type
Active-
De~cription
,
63
ADO
I/O
Both'
SYSTEM ADDRESS and DATABtls 0-15.
62
ADI
·1/0 '
Both
These' bits are used to address displ,ay memory and the 110 mapped 82C45,5 internal
61
I
AD2
I/O , "
Both
r~gi~ters. They also transfer data
betwe'en the
CPU bus and dispiay memory arid 82C455
60
AD3
"
I/O:
Both
register,s'. Addresses must be valid when output signal DATAEN is loW- and
data -musf
be
59
AD4
I/O
Both
helduntill\(GACMD (COMMAND) is low, Addresses are latched internaUY.
58
AD5
I/O
'Both
57'
AD6
I/O
Both
"
;~
Ag.~
~f/0'-'--
=Bdth-'- '
-
53
ADa
I/O
Both
52
AD9
I/O
Both
-;
..
.
-"
- _
...
51
AD10
I/O
Both
50
AD 11
I/O
Both
49
AD12
I/O
Both
48
AD13
110
Both
47
AD14
I/O
Both
,46
AD1,5
,
I/O
,Both
,
44
At6'
I'
Both
SYSTEM ADDRESS Bits 16·18 and AUXILIARY DATA BitSD-2. These bitstransler a
43
A17
I
Both
high,order address when DATAEN is low. The auxiliary data btls on pins A16,A17, and
42
A18
'
,
I
Both
At8 respectiyely are read into Bits 0-2, respectively, 01 the DIP Switch register when that
register is accessed by the CPU. The El-ddress bits -are la,tchE;!d internally and are ignored
"
lor I/O cycles.
72
\BHE
I
Low
BYTE HIGH ENABLE and AUXILIARY DATA Bit. IBHE low indicates that the high order
byte at the current
word,addr~ss:is
being
accessed.
If active. \BHE must be valid when
DATAEN is low. The pin ',is, also an-auxiliary data input which is read into Bit 3 of the DIP
Switch register when the DIP Switch register is accessed by the CPU. This data bit is
"
latched internally on the lalling edge 01 IVGACMD (lIOR).
41
ADDHI
I
High
ADDRESS HI and AUXILIARY DATA Bit. This high order memory
addre~s
eneble input is
-generated external to the 82C455 by decoding system addresses A 19-A23. As an address,
it must be valid when DATAE'N is low, is latched internally and specifies ttiat the current
memory address is valid for the 82C458. This pin is an auxliiary data bit read into Bit 4 of
the DIP- Switch register when the DIP Switch register is accessed 'by ihe CPU. this' input
I
pin is Igilored during 1/0 cyCies.
. '
67
DATAEN
0
High
DATA ENABLE. The DATAEN output controls external multiplexing 01 the system ad-
dress/data bus. DATAEN low selects address and DATAEN high selects data. In an MCA
interface, DATAEN is low when IVGACMD is high and DATAEN is high when IVGACMD is
low. In a PC or PC/AT bus interface DATAEN is low when aU IMEMR, IMEMW, IIOR, and
IIOW are high. DATAEN is high when anyone 01 IME;MR, IMEMW, \IOR or IIOW is low.
65
IRDLO
0
Low
READ LO. this output contro,ls the. direction 9f the external data transceivers on the low
order byte (Bits 0-7) of the address/data bus. It is low When data is read from the 82C455
and high when data is written to 82C455. DATAEN can be used to enable the external
transcefver.
64
IRDHI
0
Lo'w
READ' HI. This output operates in a fashion identically to the \RDLO output except that it
controls direction lor the high order byte
(B~s
8-15) 01 the address/data bus. RDHI is low
when data is read from 82C455 and high whe.n data is written to 82C455.
71
MIlO,
I
Both
MEMORY/IO or ADDRESS ENABLE and AUXILIARY DATA input. In MCA interfaces, the
(AEN)
MIlO input. pin selects either a -memory or an I/O transfer. M/IO high selects a memory
cycl~
'and low selects an 1/0 cycle. When defined as MIlO, it must be valid when the
DATAEN input is low. In PC,.Bus interfaces, this input is renamed AEN. When low, it
indicates a valid I/O address when DATAEN is low. The MilO (AEN) signal is latched
internally. In both MCA and PC-Bus environments this pin serves as an auxiliary data bit
input. It is read into Bit 5 of the DIP Switch register whenever the D[P Switch register is
accessed by the CPU.
69
ISO
I
Low
SO or, MEMORY WRITE. ISO is the memory and
VO
write input lrom the MCA bus. In
(lMEMW)
PC:Bus interface applications, this input is
nam~d.\~,sMYV.,
It must be low for CPU writes
,,"
.,
,.
"
-
,
"
to display memory.
70
lSI
I
Low
Sl or MEMORY READ. lSI is the memory and I/O read input Irom th., MeA bus. In
(IMEMR)
PC-Bus interface applications, this input is named \MEMR. It must be low to permit the
CPU to read display memory.
79
IVGASETUP
I
Low
VGA SETUP or
VO
WRITE. In an MCA environment this aclive low IVGASETUP input
(IIOW)
allows configuration registers at
[/0
Addresses -100-1 04h to be acce-ssed. All other- memory
and I/O functions are disabled. rn PC-BUS interface applications, thfs input is named .\lOW.
It must be low to permit the CPU to
wr~e
to an 82C455
VO
register,
"
68
IVGACMD
I
Low
VGA COMMAND or VO READ. In an MCA environmentthis active loW IVGACMD indicates
(IIOR)
a command bus cycle. WGACMD must not be asserted during system memory refresh
cycles. In a PC-Bus environment this input is flamed \lOR., It must be low to permit the
CPU to read an 110 registe;r.
Table 9-4 (a)
-68-
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