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9150-0125-01 R-4
4.2.8
SPI - Serial Peripheral Interface
The SPI master provides a simple CPU interface which includes a TXD register for sending data and an RXD
register for receiving data. There are up to four SPI master/ three SPI slave with EasyDMA on the Nordic
processor.
The SPI master does not implement support for chip select directly. Therefore, the CPU must use available
GPIOs to select the correct slave and control this independently of the SPI master. The SPI master supports SPI
modes 0 through 3.
Mode
Clock Polarity Clock Phase
SPI_MODE0 0(Leading)
SPI_MODE1 0(Leading)
SPI_MODE2 1(Trailing)
SPI_MODE3 1(Trailing)
The different signals SCK, MOSI, and MISO associated with the SPI master are mapped to physical pins. This
mapping is according to the configuration specified in the PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers
respectively. If the CONNECT field of a PSEL.xxx register is set to Disconnected, the associated SPI master signal
is not connected to any physical pin. The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations
are only used as long as the SPI master is enabled, and retained only as long as the device is in ON mode.
PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured when the SPI master is disabled.
To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral as
described in GPIO configuration on page 399 prior to enabling the SPI. The SCK must always be connected to a
pin, and that pin's input buffer must always be connected for the SPI to work. This configuration must be
retained in the GPIO for the selected IOs as long as the SPI is enabled. Only one peripheral can be assigned to
drive a particular GPIO pin at a time, failing to do so may result in unpredictable behavior.
For more detailed info, refer to the Nordic Semiconductor nRF52840-CKAA datasheet.
4.2.9
UART - Universal asynchronous receiver / transmitter
There are two UARTs on the Nordic processor. One of the UARTs is not available, as it is used by the Nordic
processor and the satellite transmitter.
The UART implements support for the following features:
• Full-duplex operation
• Automatic flow control
• Parity checking and generation for the 9th data bit
As illustrated in UART configuration on page 500, the UART uses the TXD and RXD registers directly to transmit
and receive data. The UART uses one stop bit.
Note: External crystal oscillator must be enabled to obtain sufficient clock accuracy for stable communication.
See CLOCK — Clock control on page 82 for more information.
The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD
associated with the UART are mapped to physical pins according to the configuration specified in the PSEL.RXD,
PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively.
If the CONNECT field of a PSEL.xxx register is set to Disconnected, the associated UART signal will not be
connected to any physical pin. The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their
configurations are only used as long as the UART is enabled, and retained only for the duration the device is in
ON mode. PSEL.RXD, PSEL.CTS, PSEL.RTS and PSEL.TXD must only be configured when the UART is disabled.
To secure correct signal levels on the pins by the UART when the system is in OFF mode, the pins must be
configured in the GPIO peripheral as described in Pin configuration on page 500. Only one peripheral can be
assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. If flow
control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the time.
ST150M User Manual
0(Active High)
1(Active Low)
0(Active High)
1(Active Low)
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