Appendix A Specifications - National Instruments IMAQ PXI-1407 User Manual

Appendix A Specifications
External Connections
Internal Pixel Clock
PCI Interface
IMAQ PCI/PXI-1407 User Manual
Trigger sense...........................................TTL
Trigger level ...........................................Programmable (rising or falling)
CSYNC sense .........................................TTL
CSYNC level ..........................................Programmable (rising or falling)
Minimum pulse width.............................50 ns
V (TTL) ...............................................2 V
IH
V (TTL)................................................0.8 V
IL
Generated frequency...............................11.66 to 15.78 MHz
Aspect correction for
standard video sources............................–5% to +7%
Pixel jitter ...............................................< 5 ns peak
PCI initiator (master) capability .............Supported
PCI target (slave) capability ...................Supported
Data path.................................................32 bits
Card voltage............................................5 V only
Card type.................................................32-bit half-size card
Parity generation/checking,
error reporting.........................................Supported
Target decode speed ...............................Medium (1 clock)
Target fast back-to-back capability ........Supported
Resource locking ....................................Supported as a master and slave
PCI interrupts..........................................Interrupts passed on
INTA# signal
A-2 www.ni.com