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13 Layout Guidelines
The layout for this device must be designed carefully. Design outside these guidelines can affect the ADC
accuracy and EMI performance. Care must be taken in the layout of signals to and from the device to avoid
coupling noise onto sensitive inputs. The layout of ground and power connections, as well as communication
signals should also be made carefully.
13.1 Ground Planes
It is very important to establish a clean grounding scheme to ensure best performance of the device. There are 3
ground pins (AVSS, DVSS, CVSS) for the device's internal power supplies and 1 ground reference (REFHM) for
the precision reference. There are noisy grounds and quiet grounds that shall be separated in the layout initially
and re-joint together in a lower PCB layer. The external components (e.g. bypass capacitors) shall be tied to the
proper grounding group if possible to keep the separation of noisy and quiet grounds apart.
•
AVSS ground:
– Bypass capacitor for these pins: BAT, VC0, CB0, LDOIN, TSREF
– Package lower pad
•
DVSS ground:
– Bypass capacitor for DVDD
– GPIO filter capacitor (if used). It can also connect to AVSS ground plane if needed
•
CVSS ground:
– Bypass capacitor for CVDD
– The bypass capacitors for COMHP/N and COMLP/N
•
REFHM ground:
– Bypass capacitor for REFHP
– If possible, separate out REFHM from AVSS on the signal connection layer and reconnect REFHM to the
AVSS ground plane on a lower layer
Even on a PCB layer that is mainly for signal routing, it is good practice to have as small an island of ground
pour as possible to provide a low impedance ground, rather than simply via down the ground trace to an lower
ground plane.
SLVAE87A – DECEMBER 2020 – REVISED OCTOBER 2023
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BQ7961x-Q1 Design Recommendations for High Voltage Automotive BMS
Copyright © 2023 Texas Instruments Incorporated
Layout Guidelines
39
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