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4 Design Files
4.1 Schematics
To download the schematics, see the design files at TIDA-010037.
4.2 Bill of Materials
To download the bill of materials (BOM), see the design files at TIDA-010037.
4.3 PCB Layout Recommendations
For this design, the following general guidelines must be followed:
•
Place decoupling capacitors close to their associated pins.
•
Use ground planes instead of ground traces and minimize the cuts in the ground plane, especially near the
ADS131M04. In this design, there is a ground plane on both the top and bottom layer; for this situation,
ensure that there is good stitching between the planes through the liberal use of vias.
•
Keep the two traces to the inputs of an ADC channel symmetrical and as close as possible to each other.
•
Crosstalk from the voltage to current channels can reduce accuracy at lower currents if power offset is not
performed. To minimize voltage to current crosstalk on the PCB, assign ADC channels 0 and 1 to the current
channels and channels 2 and 3 to the voltage channels or assign ADC channels 0 and 1 to the voltage
channels and channels 2 and 3 to the current channels.
•
For the ADS131M04 device, place the 0.1-μF capacitor closest to the AVDD pin than the 1-μF capacitor. Do
the same thing also for the 0.1-μF and 1-μF capacitors connected to DVDD.
•
Note that the order of the AINxP and AINxN pins on the ADS131M04 switches when going from one
converter to another. This swapped order is dealt with in this design by swapping the connection order of the
wires connected to the voltage and current terminals (the order of wires is reversed between J26 and J27
current terminals and it is also reversed between J28 and J29 voltage terminals)
•
Minimize the length of the traces used to connect the crystal to the microcontroller. Place guard rings around
the leads of the crystal and ground the crystal housing. In addition, there must be clean ground underneath
the crystal and placing any traces underneath the crystal must be avoided. Also, keep high-frequency signals
away from the crystal.
•
Use wide traces for power-supply connections.
•
Use a different ground plane for the isolated RS-232 and RS-485. This other ground plane is at the potential
of the RS-232 and RS-485 ground and not the GND used elsewhere in the board.
•
Ensure that the recommended clearance and creepage spacing are met for the ISO7731B and ISO7720
isolation devices in this design.
4.3.1 Layout Prints
To download the layer plots, see the design files at TIDA-010037.
4.4 Altium Project
To download the Altium Designer
4.5 Gerber Files
To download the Gerber files, see the design files at TIDA-010037.
4.6 Assembly Drawings
To download the assembly drawings, see the design files at TIDA-010037.
TIDUEM8B – MARCH 2019 – REVISED FEBRUARY 2021
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project files, see the design files at TIDA-010037.
High-Accuracy Split-Phase CT Electricity Meter Reference Design Using
Copyright © 2021 Texas Instruments Incorporated
Design Files
57
Standalone ADCs
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