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Texas Instruments GTLP User Manual

Texas Instruments GTLP User Manual

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GTLP Evaluation Module
(EVM)
User's Guide
June 2001
Standard Linear & Logic

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Summary of Contents for Texas Instruments GTLP

  • Page 1 GTLP Evaluation Module (EVM) User’s Guide June 2001 Standard Linear & Logic...
  • Page 2 Printed in U.S.A. SCEA023 0601...
  • Page 3 GTLP Evaluation Module (EVM) User’s Guide SCEA023 June 2001 Printed on Recycled Paper...
  • Page 4 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.

  • Page 5: Gtlp Evm Board Typical Test And Setup Configuration

    Preface Read This First About This Manual Use this manual to set up and use the GTLP evaluation module (EVM) for the SN74GTLPH1655 and other GTLP devices. How to Use This Manual This document contains the following chapters: Chapter 1 – Introduction Chapter 2 –...
  • Page 6 Trademarks TI-OPC is a trademark of Texas Instruments. Trademarks are the property of their respective owners.

  • Page 7: Table Of Contents

    Contents Contents Introduction ..............GTLP EVM Overview .
  • Page 8 Contents Waveform Measurement and Interpretation ........Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2) .
  • Page 9 Figures Figures 2–1 GTLP EVM Case ............. 2–2 GTLP EVM Top Tray .
  • Page 10 Figures 3–1 Tektronix O-Scope Front (Left) and Top (Right) ........3–2 O-Scope Probe Monitor-Point Adapters .
  • Page 11 Tables Tables 2–1 GTLP EVM Group Assignment ..........2–2 GTLP EVM Backplane Eight-Layer Stackup .
  • Page 12 Tables...

  • Page 13: Introduction

    Chapter 1 Introduction The Texas Instruments (TI) GTLP evaluation module (EVM) board is used to evaluate the SN74GTLPH1655 in multipoint data-transmission applications in a heavily loaded backplane. The GTLP EVM is a 17.9-in., 20-slot, 0.94-in.-pitch, 8-layer PC backplane board that provides a total of 48 parallel data lines divided into 6 groups of 8 bits staggered into various lengths.

  • Page 14: Gtlp Evm Overview

    GTLP EVM Overview 1.1 GTLP EVM Overview The EVM can be used to evaluate device parameters, while acting as a guide for high-speed board layout. Because GTLP operates over a wide range of frequencies, designers must optimize their designs for the frequency of interest.

  • Page 15: Gtlp Evm Kit Contents

    GTLP EVM Kit Contents 1.2 GTLP EVM Kit Contents This EVM kit comprises the following major parts, components of which are listed in Appendix A.1, GTLP EVM Bill of Materials: GTLP EVM kit documentation (this document, SCEA023) Backplane Clock driver card Termination card Monitored receiver card Monitored driver card...

  • Page 16: Gtlp Evm Kit Availability

    GTLP EVM Kit Availability 1.3 GTLP EVM Kit Availability The GTLP EVM kit is not available for resale, but can be obtained and used for short periods of time by contacting the GTLP team at GTLP@list.ti.com. There are six locations worldwide where GTLP EVMs can be obtained: Europe, China, Korea, Japan, and the Americas (2).
  • Page 17 Chapter 2 GTLP EVM Board Typical Test and Setup Configuration This chapter describes the GTLP EVM setup and the configurations used to evaluate the SN74GTLPH1655 transceiver. These configurations can be used to evaluate different transceivers that will be available in the future. Topic Page GTLP EVM Case...

  • Page 18: Gtlp Evm Case

    GTLP EVM Case 2.1 GTLP EVM Case The EVM is stored and transported in a sturdy plastic case with rollers and extensible handle (see Figure 2–1). The handle locks in position and can be extended or retracted by pressing the release on the underside of the handle. Figure 2–1.

  • Page 19: Gtlp Evm Top Tray

    Top Tray 2.2 Top Tray The top tray fits snuggly in the GTLP EVM case (see Figure 2–2) and holds the backplane board, power supply, extra clock crystals, and extra termination cards in place. The tray is electrostatic protective foam that holds the backplane board during demonstrations.

  • Page 20: Gtlp Evm Backplane Board

    Backplane Board 2.3 Backplane Board The backplane board (see Figure 2–3) is typical of backplanes used in commercial applications, and consists of 20 slots with 0.94-in. pitch and 48 data bits, and 1 clock bit on stripline transmission lines. Figure 2–3. GTLP EVM Backplane Board This backplane board is constructed uniquely of six groups of eight data bits each to study the effect of different backplane lengths and driver/receiver placements.

  • Page 21: Gtlp Evm Backplane Block Diagram

    Backplane Board Figure 2–4. GTLP EVM Backplane Block Diagram Backplane Overview É É É É É É É É É É É É É É É É É É Clock Generator X = Termination Card on Back of Connector Table 2–1. GTLP EVM Group Assignment Group 6 Group 5 Group 4...

  • Page 22: Gtlp Evm Backplane Eight-Layer Stackup

    Backplane Board A logic selection line (MODESEL) connects P1-1 through P1-20. The driver card uses this line to select between source-synchronous and system-clock operation. The demonstration board is an eight-layer board with separate V and ground planes. The backplane board stackup is shown in Table 2–2. Embedded microstrip nominal line width is 0.006 in., dielectric material is Nelco N4000-13 with a dielectric constant (50% resin contents) of 3.80 @ 100 MHz.

  • Page 23: Gtlp Evm Group 1, Bits 1 Through 8 Trace Impedance

    Backplane Board Targeted, nominal, unloaded line impedance was 50 Ω, but, based on post-manufacturing testing, was not consistent. Results for Group 1, bits 1 through 8 are shown in Table 2–3. The backplane natural trace impedance (Z is calculated and is a best estimate. The backplane trace impedance with only ′) and the backplane the connector pins attached (i.e., all cards removed) (Z ′′) are...

  • Page 24: Connectors

    Connectors 2.4 Connectors An AMP Z-PACK 2-mm, 110-pin, hard-metric (HM) male connector is used in slots 1 through 20 (see Figure 2–5) . Figure 2–5. AMP Z-PACK 2-mm, 110-Pin, Hard-Metric (HM) Male Connector Five pins are used on the backplane, with three different lengths on the backplane daughter-card side.

  • Page 25: Amp Pin Lengths

    Connectors Figure 2–6. AMP Pin Lengths * X, U, V are used only for cross-connect applications. Not all versions are tooled. GTLP EVM Board Typical Test and Setup Configuration...

  • Page 26: Amp Single-Line-Model Data Sheet

    Connectors Figure 2–7. AMP Single-Line-Model Data Sheet 2-10...

  • Page 27: Power Supply (Left) And Backplane Connection (Right)

    Power Supply 2.5 Power Supply The power supply (see Figure 2–8) is a universal power supply that accepts 100 V to 240 V, 50/60-Hz ac and uses any wall plug that connects to the IEC 320 two-connector universal socket with the US/Canada Edison plug. An alternate supply cord with a different wall plug must be procured locally, if required.

  • Page 28: Tt Linear Regulator

    Power Supply The 3.3 V is further reduced to 1.5 V, 7.5 A by the LT1083CP linear regulator (see Figure 2–9) for the termination voltage (V ). V is set by the combination of R1 and R2 and can be varied in the factory between 0.8 V to 1.8 V, but is set at 1.0 V for field use at GTLP levels.

  • Page 29: Power-Supply Led Indicators

    Power Supply Figure 2–10. Power-Supply LED Indicators GTLP EVM Board Typical Test and Setup Configuration 2-13...

  • Page 30: Clock Crystals

    Clock Crystals 2.6 Clock Crystals Clock frequency is controlled by the clock-driver card and is limited by clock-control components to 100 MHz. The GTLP receiver device is used in a latched mode of operation, so GTLP data frequency is equal to one-half the clock frequency.

  • Page 31: Termination Cards

    Termination Cards 2.7 Termination Cards Because proper backplane termination has a large effect on signal integrity and is investigated easily, Group 1 has removable termination cards on the back of the backplane (see Figure 2–13). The termination cards are identical, except for the resistor values that are 25 Ω, 33 Ω, 38 Ω, or 50 Ω.

  • Page 32: Termination-Card Stackup

    Termination Cards Table 2–4. Termination-Card Stackup Copper Physical Dielectric Dielectric Trace Name Layer Weight (oz) Representation Height (in.) Name Data signal 0.004 B stage plane plane 0.004 Core Ground plane Ground plane 0.004 B stage Bottom Data signal Groups 2 through 6 have 25-Ω fixed termination resistors due to space limitations, and have one bypass capacitor for every four termination resistors.

  • Page 33: Bottom Compartment

    Bottom Compartment 2.8 Bottom Compartment The portable oscilloscope and backplane daughter cards are stored under the top tray of the GTLP EVM case (see Figure 2–15). Figure 2–15. Oscilloscope and Backplane Daughter-Card Storage Area Clock Cards Unmonitored Monitored Receiver Receiver Cards Cards Empty...

  • Page 34: Measurement Equipment

    Measurement Equipment 2.9 Measurement Equipment The Tektronix THS730A Oscilloscope/DMM (O-Scope) (see Figure 2–16) can be stored in the bottom of the case (see Figure 2–15). It is easy to operate and is portable. The O-Scope can monitor two channels simultaneously. Store the O-Scope face down to prevent damage to the buttons during transit.

  • Page 35: Clock Cards

    Clock Cards 2.10 Clock Cards Two clock cards (see Figure 2–17) are included with the EVM, one primary and one spare. The clock cards generate the clock signal that is sent to every slot via mitered lines, so that the clock arrives at exactly the same time at each card.

  • Page 36: Clock-Card Stackup

    Clock Cards Table 2–5. Clock-Card Stackup Copper Physical Dielectric Dielectric Trace Name Layer Weight (oz) Representation Height (in.) Name Data signal 0.004 B stage plane plane 0.004 Core Ground plane Ground plane 0.004 B stage Bottom Data signal 2-20...

  • Page 37: Driver-Card Stackup

    Driver Cards 2.11 Driver Cards Separate driver and receiver daughter cards were manufactured for use on the backplane because, even though the bidirectional SN74GTLPH1655 device is used, each type of card is hardwired to operate in a certain direction. The driver card generates a data pattern from the system clock and drives the GTLP lines on the backplane.

  • Page 38: Gtlp Evm Driver Daughter Card

    Driver Cards The driver daughter card (see Figure 2–18) has SMB monitor points for selected LVTTL and GTLP signals, in addition to jumpers for Group 1, bit 1 switching (JB1), system or SN74GTLP1394 source-synchronous clock selection (JB2), and selection of the SN74GTLPH1655 slow or fast edge rate (JB3).

  • Page 39: Single-Bit Selection

    Driver Cards 2.11.1 Single-Bit Selection JB1 three-position jumper is used to set Group 1, bit 1 to pass the normal data pattern, set the signal low, or set the signal high (see Figure 2–19). The JB1 jumper is stored on the lowest pin (see Figure 2–19) when set high, to prevent losing it.

  • Page 40: Edge-Rate Control

    Driver Cards 2.11.2 Edge-Rate Control The device used as the backplane driver, SN74GTLPH1655, has a feature by which the backplane slew rate is adjustable via an external edge-rate-control (ERC) pin held at 3.3 V (slow) or GND (fast). The ERC is set by the JB3 jumper located below the bit-selection jumper and has two positions: not connected is slow, and shorted is fast (see Figure 2–20).

  • Page 41: Source-Synchronous Clock/System-Clock Selection

    Driver Cards 2.11.3 Source-Synchronous Clock/System-Clock Selection Backplanes usually have a system-wide synchronous clock. A system clock provides an absolute reference time signal from the clock card to every daughter card at exactly the same time. Source-synchronous clock operation is different because it allows the absolute system clock to be sent by the backplane driver along with the data.

  • Page 42: Receiver-Card Stackup

    Receiver Cards 2.12 Receiver Cards Receiver cards place a load on the backplane and provide a point to monitor the signals. There are two types of receiver cards: one that has built-in monitor points, and one with no monitor points. Either type can be placed in any slot in the backplane, typically with the monitored receiver card placed in the slots under observation.
  • Page 43 Receiver Cards Figure 2–22 shows a monitored receiver card. Monitor points on the right side are for GTLP Groups 1, 2, 3, 4, 5, and 6. Monitor points on the top are for LVTTL latch clock, Groups 6, 5, 4, 3, 2, and 1. The LVTTL latch-clock source is either the system clock or source-synchronous clock.

  • Page 44: Gtlp Evm Monitored Receiver Card

    Receiver Cards Figure 2–22. GTLP EVM Monitored Receiver Card TP13 TP12 TP11 TP10 TP9 TP8 Note: SN74GTL1655 devices were used on the receiver cards. The SN74GTLPH1655 was in development and initial preproduction samples were used for the driver cards, but insufficient quantities were available for the receiver cards.

  • Page 45: Backplane Setup

    Backplane Setup 2.13 Backplane Setup 2.13.1 Insertion of Clock Cards The clock-card connectors (see Figure 2–23) use AMP 55-pin, 2-mm, HM connectors and are identical to the backplane termination-card connectors. They can be mated improperly because they are keyed only on one side, whereas the backplane connectors are keyed in the center and do not allow improper insertion.

  • Page 46: Connector Premate (Left), Mating (Center), And Mated (Right)

    Backplane Setup Figure 2–24. Connector Premate (Left), Mating (Center), and Mated (Right) Figure 2–25 (left) shows the clock card properly inserted, with the CDC components and the clock crystal facing away from the backplane connectors and daughter cards. Yellow dots are located on the connector and the card to help ensure proper orientation.

  • Page 47: Insertion Of Clock Crystals

    Backplane Setup 2.13.2 Insertion of Clock Crystals Clock crystals are live insertable, unlike the clock card, which is not live insertable. Clock crystals are inserted easily on the clock card by pulling off one crystal and inserting the new crystal (see Figure 2–26). The leads can be bent gently to ease insertion.

  • Page 48: Insertion Of Termination Cards

    Backplane Setup 2.13.3 Insertion of Termination Cards Termination-card, AMP Z-PACK, 2-mm, 55-pin, HM male and female connectors are identical to the clock-card connectors, and are inserted directly onto the K and T pins used for slots 1 and 20, V , and data bits.

  • Page 49: Insertion Of Driver And Receiver Cards

    Backplane Setup 2.13.4 Insertion of Driver and Receiver Cards The driver and receiver cards are live insertable and are easy to insert and remove, although some slight side-to-side rocking action might be required. The cards can be inserted into any slot in any order, but only one driver card should be used at any one time.

  • Page 50: Close-Up View Of Connector Keying

    Backplane Setup Figure 2–30. Close-up View of Connector Keying Wide Key Narrow Key The card should be placed squarely on the connector and pressed down (see Figure 2–31), with very little side-to-side motion. The components are facing left towards slot 1, the power supplies are on the top/right, and the Group 1–6 markings are on the bottom/left.

  • Page 51: Connectors Properly Mated

    Backplane Setup Figure 2–32. Connectors Properly Mated GTLP EVM Board Typical Test and Setup Configuration 2-35...

  • Page 52: Oscilloscope Operation

    Chapter 3 Oscilloscope Operation Topic Page Oscilloscope Setup ......... . . Measurements .

  • Page 53: Oscilloscope Setup

    Oscilloscope Setup 3.1 Oscilloscope Setup The recommended oscilloscope (O-Scope) for the GTLP EVM is the Tektronix THS730A (see Figure 3–1). It allows only two-channel operation, which should be sufficient for most investigations done with the demonstration backplane. Figure 3–1. Tektronix O-Scope Front (Left) and Top (Right) SMB adapters (see Figure 3–2) are needed to properly mate Tektronix probes with the test points.

  • Page 54: Measurements

    Measurements 3.2 Measurements The first step in taking measurements is to plug one probe into channel 1 (CH 1) of the O-Scope and connect the opposite end to the desired monitor point. Plug the other probe into channel 2 (CH 2) of the O-Scope and connect the opposite end to the desired monitor point (see Figures 3–1 and 3–3).

  • Page 55: O-Scope Display

    Measurements Waveforms similar to those in Figure 3–5, depending on how the O-Scope presets were set, are displayed. In Figure 3–5, CH 2 is selected. Figure 3–5. O-Scope Display...

  • Page 56: Timing Adjustment

    Measurements To adjust the timing (x or horizontal axis), press the appropriate side of the SEC/DIV button (see Figure 3–6). An example of the results is shown for 50 ns/division and 100 ns/division. Timing is the same for both channels and is independent of channel selection.

  • Page 57: Trigger Adjustment

    Measurements To adjust the trigger, press the MENU button (see Figure 3–8), then press Trigger Source to display a submenu. In the submenu, select Ch1, Ch2, or Ext [DMM] by repeatedly pressing the same Trigger Source button. After the appropriate trigger is selected, press the CLEAR MENU button to restore the O-Scope to operation.

  • Page 58: Waveform Measurement And Interpretation

    Chapter 4 Waveform Measurement and Interpretation In this chapter, five different measurement cases are discussed in detail, and several more measurement combinations are outlined. Many other combinations are possible. Topic Page Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2) .

  • Page 59: Timing Relationship Of Driver Card (D1) Data Pattern (Ch1) And Driver Card (D1) Latch Clock (Ch2)

    Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2) 4.1 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2) Figure 4–1 shows the probe hookup and related O-Scope output for Case 1. The LVTTL latch clock signal goes to the SN74GTLPH1655 driving device CLK pin, and the LVTTL data signal goes to the A-port input pin, specifically the Group 1, bit 1 data signal.

  • Page 60: Timing Relationship Of Driver Card (D1) Data Pattern (Ch1) And Driver Card (D1) Group 1 Gtlp Data Out (Ch2)

    Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Group 1 GTLP Data Out (Ch2) 4.2 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Group 1 GTLP Data Out (Ch2) Figure 4–2 shows the probe hookup and O-Scope output for Case 2. The LVTTL data goes into the SN74GTLPH1655 driving device A-port input, and the GTLP data comes out of the B-port output.

  • Page 61: Timing Relationship Of Driver Card (D1) Data Pattern (Ch1) And Receiver Card (R2) Group 1 Gtlp Data In (Ch2)

    Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Receiver Card (R2) Group 1 GTLP Data In (Ch2) 4.3 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Receiver Card (R2) Group 1 GTLP Data In (Ch2) Figure 4–3 shows the probe hookup and O-Scope output for Case 3. The LVTTL data input goes to the SN74GTLPH1655 driving device A-port input, and the GTLP data input goes to the SN74GTL1655 receiving device B-port in slot 2.

  • Page 62: Timing Relationship Of Driver Card (D1) Data Pattern (Ch1) And Receiver Card (R2) Group 1 Lvttl Data Out (Ch2)

    Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Receiver Card (R2) Group 1 LVTTL Data Out (Ch2) 4.4 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Receiver Card (R2) Group 1 LVTTL Data Out (Ch2) Figure 4–4 shows the probe hookup and O-Scope output for Case 4. The LVTTL data input goes to the SN74GTLPH1655 driving device A-port input, and the LVTTL data output of the SN74GTL1655 receiving device goes to A port in slot 2.

  • Page 63: Receiver Card (R20) Group 1 Gtlp Data In (Ch2)

    Timing Relationship of Receiver Card (R2) Group 1 GTLP Data In (Ch1) 4.5 Timing Relationship of Receiver Card (R2) Group 1 GTLP Data In (Ch1) and Receiver Card (R20) Group 1 GTLP Data In (Ch2) Figure 4–5 shows the probe hookup and O-Scope output for Case 5. You can see the flight-time delay between the output of the SN74GTLPH1655 driving device B port in slot 1 and the SN74GTL1655 receiving device B port in slot 20.

  • Page 64: Monitored Waveforms

    Monitored Waveforms 4.6 Monitored Waveforms There are differences in waveforms between GTLP monitor test points and measurements taken at the backplane connector pins, due to interference from LVTTL data and clock signals not shielded adequately on the daughter cards. This concern is only for this demonstration backplane because there is no reason to extend the GTLP signals past the GTLP device B-port output pins on operational daughter cards.
  • Page 65 Monitored Waveforms...

  • Page 66: Troubleshooting

    Chapter 5 Troubleshooting Topic Page Spare Parts ........... Replacing 5-A Fuse F2 .

  • Page 67: Spare Parts

    Spare Parts 5.1 Spare Parts Each EVM is equipped with spare fuses and jumpers (see Figure 5–1). Figure 5–1. Spare Fuses and Jumpers...

  • Page 68: Replacing 5-A Fuse F2

    Replacing 5-A Fuse F2 5.2 Replacing 5-A Fuse F2 Fuse F2 (see Figure 5–2) provides power from the 3.3-V switching regulator to the 3.3-V power plane and blows if V is shorted to GND. Shorting can occur if a connector pin is bent during insertion or if measurements are taken directly from the backplane.

  • Page 69: Replacing 2.5-A Fuse F1

    Replacing 2.5-A Fuse F1 5.3 Replacing 2.5-A Fuse F1 Fuse F1 (see Figure 5–3) provides power from the power supply to the 3.3-V and 5-V switching regulators and blows if the switching regulators fail. It is replaced as easily as fuse F2. Disconnect the power from the board, pull out the fuse with pliers, push in the new fuse, then reconnect the power supply.

  • Page 70: Damage To The Daughter Cards

    Damage to the Daughter Cards 5.4 Damage to the Daughter Cards The daughter cards are not field repairable and must be returned to the factory for repair. Troubleshooting...
  • Page 71 Damage to the Daughter Cards...

  • Page 72: Bill Of Materials, Schematics, Board Layouts, And Suggested Specifications

    Appendix A Appendix A Bill of Materials, Schematics, Board Layouts, and Suggested Specifications Topic Page GTLP EVM Bill of Materials ........Board Layouts and Schematics .

  • Page 73: Gtlp Evm Bill Of Materials

    GTLP EVM Bill of Materials A.1 GTLP EVM Bill of Materials Backplane Device Type Quantity Z-PAK 110-Pin Male Connector Z-PAK 55-Pin Male Connector 2.5 AMP Fuseholder 5 AMP Fuseholder Surface Mount 0.01uF Cap Surface Mount 0.1uF Cap Surface Mount Tantalum 10uF/10V Cap Surface Mount Tantalum 1uF/35V Cap Surface Mount Tantalum 47uF/10V Cap Surface Mount 100 ohm Resistor...
  • Page 74 GTLP EVM Bill of Materials Clock Driver Card Device Type Quantity Z-PAK 55-Pin Female Connector CDC2586 TQFP Clock Driver Surface Mount 0.1uF Cap Surface Mount 453 ohm Resistor Oscillator Mount SMB Coax Connector Termination Card Device Type Quantity Z-PAK 55-Pin Female Connector Surface Mount 0.1uF Cap Surface Mount 25 ohm Resistor Monitored Receiver Card...
  • Page 75 GTLP EVM Bill of Materials Monitored Driver Card Device Type Quantity Z-PAK 55-Pin Female Connector SN74ALVC126 TVSOP Buffer SN74GTLP1394 TVSOP Transceiver SN74GTLPH1655 TSSOP UBT SN74ALVCH16344 TSSOP Buffer CDC351 Clock Buffer SN74LVC112A JK Flip-Flop SN74LVC04 Inverter Surface Mount 0.1uF Cap Surface Mount 47pF Cap Surface Mount 1K ohm Resistor Surface Mount 2K ohm Resistor Surface Mount 500 ohm Resistor...

  • Page 76: Board Layouts And Schematics

    Board Layouts and Schematics A.2 Board Layouts and Schematics Figure A–1. Backplane Layout, Front Side Ç Ç Ç Ç Ç Ç Ç Ç Bill of Materials, Schematics, Board Layouts, and Suggested Specifications...

  • Page 77: Backplane Layout, Back Side

    Board Layouts and Schematics Figure A–2. Backplane Layout, Back Side Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç É É É...

  • Page 78: Driver-Card And Receiver-Card Connector Pinout

    Board Layouts and Schematics Figure A–3. Driver-Card and Receiver-Card Connector Pinout P1-X P1-1B and P1-20B Sys. Clk. 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V G1D3 G1D1 G1D4 G1D2 G1D3 G1D1 G1D4 G1D2 G1D7 G1D5 G1D8 G1D6 G1D7 G1D5 G1D8 G1D6 1.5V 1.5V 1.5V...

  • Page 79: Backplane Schematic

    Board Layouts and Schematics Figure A–4. Backplane Schematic...
  • Page 80 4.0 inches Jumper Block 1 DATA ALVCH16344 ALVCH16344 Jumper Block 3 PCJ1 GTLxxx GTLxxx GTLxxx Jumper Block 2 AMP type A 100623–1 PCJ2 J1–x OUTPUT Connector .76 inch...

  • Page 81: Driver-Card Schematic

    Board Layouts and Schematics Figure A–6. Driver-Card Schematic A-10...
  • Page 82 3.5 inches RECEIVER CARD (Standard) RTerm RTerm RTerm RTerm RTerm RTerm GTL 1655 GTL 1655 GTL 1655 AMP type A 100623–1 J1–x OUTPUT Connector .76 inch...
  • Page 83 3.5 inches TP13 TP12 TP11 TP10 RECEIVER CARD (Monitor) 10K network 10K network 10K network 10K network 10K network 10K network RTerm RTerm RTerm RTerm RTerm RTerm GTL 1655 GTL 1655 GTL 1655 AMP type A 100623–1 J1–x OUTPUT Connector .76 inch...

  • Page 84: Receiver-Card Schematic

    Board Layouts and Schematics Figure A–9. Receiver-Card Schematic Bill of Materials, Schematics, Board Layouts, and Suggested Specifications A-13...
  • Page 85 2.5 inches Monitor CLOCK CLOCK CARD CLOCK DRIVER CLOCK DRIVER AMP type C 100161–1 OUTPUT Connector .76 inch...
  • Page 86 Title .1uF Clock Card 51.1 3.3V Size Document Number Date: Thursday, March 16, 2000 Sheet 3.3V 3.3V .1uF .1uF .1uF .1uF CLK_OUT10 CLK_OUT9 CDC2586 CDC2586 CLK_OUT8 CLK_OUT11 CLK_OUT7 CLK_OUT12 .1uF .1uF .1uF .1uF CLK_OUT6 CLK_OUT5 CLK_OUT13 CLK_OUT4 CLK_OUT14 CLK_OUT3 CLK_OUT15 CLK_OUT2 CLK_OUT16 CLK_OUT1...
  • Page 87 2 inch Standard termination card AMP type C 100161–1 Output Connector...
  • Page 88 R8 R2 E8E9E1 B1B1 Z– PAK E3E2 Title Termination Card Size Document Number Date: Wednesday, December 08, 1999 Sheet...
  • Page 89 Board Layouts and Schematics A-18...

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