Processor 4/7 - Clevo P670RG Series Service Manual

Schematic Diagrams

Processor 4/7

D
Sheet 5 of 79
Processor 4/7
C
VCCST_PWRGD
B
13,40,48,61,63
A
48 H_PROCHOT_EC
B - 6 Processor 4/7
5 4
NEAR CPU
1.0V_VCCST
R322 R330
100_04 56.2_1%_04
61,63 H_CPU_SVIDDAT
61,63 H_CPU_SVIDALRT#
61,63 H_CPU_SVIDCLK
R324
220_04
H_PROCHOT#
56,61,63 H_PROCHOT#
52 DDR_VTT_PG_CTRL
VCCST_PW RGD R182
R771 20_1%_04 H_PM_DOW N_R
34 H_PM_DOW N
34 PCH_PECI
D01A
TO EC
48 H_PECI
34 PCH_THERMTRIP#
R758
FLOAT FOR SKL
GND FOR CNL
1.0V_VCCST
R188
VDD3
1K_04
VCCST_PW RGD
R174
100K_04
D
C353
G
5 *0.01u_16V_X7R_04
S Q9B
MTDK5S6R
D01A D
2 G
R1859 0_04
ALL_SYS_PW RGD
S Q9A
MTDK5S6R
C1735
*0.1u_10V_X7R_04
1.0DX_VCCSTG
H_PROCHOT# R362 1K_04
Q27
G C590
2SK3018S3
47P_50V_NPO_04
R368
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
5 4
3
?
SKYLAKE_HALO
U113E
BGA1440
B31
37 PCH_CPU_BCLK_R_DP BCLKP CFG[0]
A32
37 PCH_CPU_BCLK_R_DN
BCLKN CFG[1]
CFG[2]
D35
37 PCH_CPU_PCIBCLK_R_DP
PCI_BCLKP CFG[3]
C36
37 PCH_CPU_PCIBCLK_R_DN
PCI_BCLKN CFG[4]
CFG[5]
E31
37 CPU_24MHZ_R_DP
CLK24P CFG[6]
D31
37 CPU_24MHZ_R_DN
CLK24N CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CPU_VIDALERT_N BH31
VIDALERT# CFG[15]
BH32
VIDSCK
BH29
VIDSOUT CFG[17]
R770 499_1%_04 H_PROCHOT#_R BR30
PROCHOT# CFG[16]
D01A CFG[19]
R779 *0402_short BT13
DDR_VTT_CNTL CFG[18]
R780 *10K_04
3.3VA
BPM#[0]
BPM#[1]
BPM#[2]
60.4_1%_04 VCCST_PW RGD_CPU H13
VCCST_PWRGD BPM#[3]
BT31
35 H_PW RGD
PROCPWRGD
BP35
34 PLTRST_CPU_N
RESET# PROC_TDO
BM34
34 H_PM_SYNC PM_SYNC PROC_TDI
BP31
PM_DOWN PROC_TMS
H_PECI_R
R159 *12.1_1%_04 BT34
PECI PROC_TCK
J31
R762 *0402_short
THERMTRIP#
PROC_TRST#
H_SKTOCC_N BR33
36 H_SKTOCC_N SKTOCC# PROC_PREQ#
*0_04 BN1
PROC_SELECT# PROC_PRDY#
BM30
D01A Del test point
CATERR#
CFG_RCOMP
5 OF 14
SKL_H_BGA_BGA REV = 1
PCIE PORT BIFURCATION STRAPS
CFG[6:5]
DEFENSIVE PULL DOWN SITE
CFG7
3.3VA 32,33,34,35,36,38,40,54
1.0DX_VCCSTG 7,56,57
1.0V_VCCST 7,34,35,55,61,63
VDD3 30,32,35,38,40,44,48,50,51,53,54,55,56,57,58
VCCIO 2,3,7,55
3
2 1
CFG[0]: Stall reset sequence after PCU
PLL lock until de-asserted:
— 1 = (Default) Normal Operation;
No stall.
VCCIO
— 0 = Stall.
R781 CFG[1]: Reserved configuration lane.
CFG9 *1K_04
CFG[2]: PCI Express* Static x16 Lane
Numbering Reversal.
BN25 CFG0 R323 *1K_04
— 1 = Normal operation
BN27 CFG1 R767 *1K_04
— 0 = Lane numbers reversed.
BN26 CFG2 R325 *1K_04
BN28 CFG[3]: Reserved configuration lane.
CFG3 R768 *1K_04
BR20 CFG4 R784 1K_04
CFG[4]: eDP enable:
BM20 CFG5 R326 *1K_04
— 1 = Disabled.
BT20 CFG6 R775 *1K_04
— 0 = Enabled.
BP20 CFG7 R766 *1K_04
CFG[6:5]: PCI Express* Bifurcation
BR23
CFG8 R761 *1K_04
— 00 = 1 x8, 2 x4 PCI Express*
BR22 CFG9 R774 *1K_04
— 01 = reserved
BT23 CFG10 R776 *1K_04
— 10 = 2 x8 PCI Express*
BT22 CFG11 R759 *1K_04
— 11 = 1 x16 PCI Express*
BM19 CFG12 R327 *1K_04
BR19 CFG13 R765 *1K_04 CFG[7]: PEG Training:
BP19 CFG14 R782 *1K_04 — 1 = (default) PEG Train
BT19 CFG15 R783 *1K_04 immediately following RESET# de
assertion.
BN23
— 0 = PEG Wait for BIOS for
BP23 Del test point D01A
training.
BP22
CFG[19:8]: Reserved configuration
BN22
lanes.
SKL_XDP_MBP_0
BR27
BT27 SKL_XDP_MBP_1
BM31 SKL_MBP_2
BT30 SKL_MBP_3
BT28 H_TDO
BL32
1.0V_VCCST
BP28 Del test point D01A
H_TCK
BR28
H_TDO
R788 51_04
BP30 H_TRST#
H_TRST# 40
BL30 H_PREQ# H_TCK R348 51_04
H_PREQ# 40
BP27 H_PRDY#
H_PRDY# 40
BT25 CFG_RCOMP
3.3VA
H_SKTOCC_N
R772 100K_04
R786
49.9_1%_04
?
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
CFG4 AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[05]Processor 4/7-CLK/JTAG/MISC [05]Processor 4/7-CLK/JTAG/MISC [05]Processor 4/7-CLK/JTAG/MISC
Size Size Size Document Number Document Number Document Number
6-71-P65R0-D03 6-71-P65R0-D03 6-71-P65R0-D03
A3 A3 A3 P650RE P650RE P650RE
Date: Date: Date: Friday, July 03, 2015 Friday, July 03, 2015 Friday, July 03, 2015 Sheet Sheet Sheet
2 1
D
C
B
A
Rev Rev Rev
D03 D03 D03
5 5 5 of of of 79 79 79