Working Principle And Signal Flow - Huawei ATN 950B Hardware Description

ATN 950B Multi-service Access Equipment
Hardware Description
Function and Feature Remarks
ML-PPP
NOTE

5.8.3 Working Principle and Signal Flow

The AND2MD1A/AND2MD1B mainly consists of the service access module, service
processing module, management module, clock module, and power supply module.
Figure 5-16
Figure 5-16 Functional block diagram of the AND2MD1A/AND2MD1B
Issue 03 (2012-07-23)
a: In the case of the AND2MD1A/AND2MD1B, the links corresponding to the former 16 and latter 16 E1
ports cannot be bundled to an IMA group.
a: In the case of the AND2MD1A/AND2MD1B, the links corresponding to the former 16 and latter 16 E1
ports cannot be bundled to an ML-PPP group.
shows the functional block diagram of the AND2MD1A/AND2MD1B.
32 x E1
Service access
module
Line clocks
Clock
module
Line clocks
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Supports the timeslot compression function. Provides the vacant
64 kbit/s timeslot suppression function for the CES services in the
CESoPSN mode to save the transmission bandwidth.
The jitter compensation buffer time of the CES service can be set.
The jitter buffer time ranges from 2 ms to 8 ms.
The packet loading time of the CES service can be set. The
encapsulation buffer time ranges from 1 ms to 3 ms.
Number of supported ML-PPP
groups
Maximum number of links
supported by each ML-PPP
group
Functions as the UNI interface to access IP packets of the L3VPN
services.
Service signal Service
processing
Management bus
Management
module
3.3V
. .
. .
. .
module
1V
5 Physical Interface Card
16
b
16
Service signal
module
Management bus
-48V/-60V
Power
supply
-48V/-60V
System clocks
Backplane
CXP
CXP
System power
supply
System power
supply
CXP
CXP
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