GE Multilin GEK-113000T User Manual page 248

APPENDIX C
SETPOINT>RELAY CONFIGURATION>PROTECTION ELEMENTS
PROTECTION ELEMENT SOURCE
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC3 HIGH A BLK
PHASE DIR3 A OP
LATCHED VIRT IP 1
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC3 HIGH B BLK
PHASE DIR3 B OP
LATCHED VIRT IP 1
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC3 HIGH C BLK
PHASE DIR3 C OP
LATCHED VIRT IP 1
GROUP 1 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC1 LOW A BLK
PHASE DIR1 A OP
LATCHED VIRT IP 2
GROUP 1 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC1 LOW B BLK
PHASE DIR1 B OP
LATCHED VIRT IP 2
GROUP 1 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC1 LOW C BLK
PHASE DIR1 C OP
LATCHED VIRT IP 2
GROUP 2 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC2 LOW A BLK
PHASE DIR2 A OP
LATCHED VIRT IP 2
GROUP 2 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC2 LOW B BLK
PHASE DIR2 B OP
LATCHED VIRT IP 2
GROUP 2 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC2 LOW C BLK
PHASE DIR2 C OP
LATCHED VIRT IP 2
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC3 LOW A BLK
PHASE DIR3 A OP
LATCHED VIRT IP 2
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC3 LOW B BLK
PHASE DIR3 B OP
LATCHED VIRT IP 2
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PH IOC3 LOW C BLK
PHASE DIR3 C OP
LATCHED VIRT IP 2
GEK-113000T
C.2 FACTORY DEFAULT CONFIGURATION
F650 Digital Bay Controller
SIGNAL LOGIC SOURCE LOGIC
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
C
C-23