Supermicro SuperStorage 2029P-E1CR48H User Manual page 38

Note: Please refer to the drawing on the next page for the locations of DIMM modules.
Symmetric Population within 1 CPU Socket
P1- P1- P1-
Modes
DIMMF1 DIMMF2 DIMME1
AD DRAM1 DCPMM DRAM1
MM DRAM1 DCPMM DRAM1
AD + MM DRAM3 DCPMM DRAM3
AD DRAM1 - DRAM1
MM DRAM2 - DRAM2
AD + MM DRAM3 - DRAM3
AD DRAM1 - DRAM1
MM DRAM1 - DRAM1
AD + MM DRAM3 - DRAM3
AD DCPMM - DRAM1
MM DCPMM - DRAM1
AD + MM DCPMM - DRAM3
AD DCPMM - DRAM1
Asymmetric Population within 1 CPU Socket
P1- P1- P1-
Modes
DIMMF1 DIMMF2 DIMME1
AD DRAM1 - DRAM1
AD* DRAM1 - DRAM1
DDR4 Type
DRAM1
RDIMM
DRAM2 RDIMM
DRAM3 RDIMM
Note: DDR4 single rank x8 is not available for DCPMM Memory Mode or App-Direct Mode.
Capacity
DCPMM
•
* 2nd socket has no DCPMM DIMM
•
For MM, general NM/FM ratio is between 1:4 and 1:16. Excessive capacity for FM can be used for AD. (NM = Near
Memory; FM = Far Memory)
•
For each individual population, rearrangements between channels are allowed as long as the resulting population is
compliant with the PDG rules for the 82xx/62xx/52xx/42xx platform.
•
For each individual population, please use the same DDR4 DIMM in all slots.
•
For each individual population, sockets are normally symmetric with exceptions for 1 DCPMM per socket and 1 DCPMM
per node case. Currently, DCPMM modules operate at 2666 MHz.
•
No mixing of DCPMM and NVMDIMMs within the same platform is allowed.
•
This DCPMM population guide targets a balanced DCPMM-to-DRAM-cache ratio in MM and MM + AD modes.
Chapter 3: Maintenance and Component Installation
P1- P1- P1- P1-
DIMME2 DIMMD1 DIMMD2 DIMMA2
DCPMM DRAM1 DCPMM DCPMM
DCPMM DRAM1 DCPMM DCPMM
DCPMM DRAM3 DCPMM DCPMM
- DRAM1 DCPMM DCPMM
- DRAM2 DCPMM DCPMM
- DRAM3 DCPMM DCPMM
DCPMM DRAM1 DCPMM DCPMM
DCPMM DRAM1 DCPMM DCPMM
DCPMM DRAM3 DCPMM DCPMM
- DRAM1 - -
- DRAM1 - -
- DRAM3 - -
DRAM1 DRAM1 DRAM1 DRAM1
P1- P1- P1- P1-
DIMME2 DIMMD1 DIMMD2 DIMMA2
- DRAM1 - DCPMM
- DRAM1 - DCPMM
Legend (for the two tables above)
3DS RDIMM LRDIMM 3DS LRDIMM
-
3DS RDIMM LRDIMM
Legend (-for the two tables above)
Any Capacity (Uniformly for all channels for a given configuration)
38
P1- P1- P1-
DIMMA1 DIMMB2 DIMMB1 DIMMC2
DRAM1 DCPMM DRAM1 DCPMM
DRAM1 DCPMM DRAM1 DCPMM
DRAM3 DCPMM DRAM3 DCPMM
DRAM1 - DRAM1
DRAM2 - DRAM2
DRAM3 - DRAM3
DRAM1 DCPMM DRAM1
DRAM1 DCPMM DRAM1
DRAM3 DCPMM DRAM3
DRAM1 - DRAM1
DRAM1 - DRAM1
DRAM3 - DRAM3
DRAM1 DRAM1 DRAM1
P1- P1- P1-
DIMMA1 DIMMB2 DIMMB1 DIMMC2
DRAM1 - DRAM1
DRAM1 - DRAM1
Capacity
Any Capacity
-
Refer to Validation Matrix (DDR4 DIMMs
validated with DCPMM) below.
-
P1- P1- Channel
DIMMC1 Config.
DRAM1 2-2-2
DRAM1 2-2-2
DRAM3 2-2-2
- DRAM1 2-1-1
- DRAM2 2-1-1
- DRAM3 2-1-1
- DRAM1 2-2-1
- DRAM1 2-2-1
- DRAM3 2-2-1
- DCPMM 1-1-1
- DCPMM 1-1-1
- DCPMM 1-1-1
- DCPMM 2-2-1
P1- P1- Channel
DIMMC1 Config.
- DRAM1 2/1-1-1
- DRAM1 2/1-1-1