Power Supply Recommendations - SG Micro SGM5200 Manual

12-bit, 1msps, 16 channels, single-ended, serial interface adc

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Table of Contents

SGM5200

APPLICATION INFORMATION (continued)

Another option is to add a common ADC driver buffer

between the MXO and AINP pins, see Figure 18. This

relaxes the restriction on source impedance to a large

extent. Refer to Typical Characteristics section for the effect

of source impedance on device performance. The typical

characteristics show that the device has respectable

performance with up to 1kΩ source impedance. This

topology (including a common ADC driver) is useful when

all channel signals are within the acceptable range of the

ADC. In this case the user can save on signal conditioning

circuit for each channel.

When the converter samples an input, the voltage

difference between AINP and AGND is captured on the

internal capacitor array. The (peak) input current through

the analog inputs depends upon a number of factors:

sample rate, input voltage and source impedance. The

current into the SGM5200 charges the internal capacitor

array during the sample period. After this capacitance has

High Input Impedance PGA

(or Non-Inverting Buffer

Such as SGM8604-1)

Figure 18. Typical Application Diagram Showing Common Buffer/PGA for All Channels

SG Micro Corp

www.sg-micro.com

MXO

CH0

CH1

CH2

CH15

REF

SGM4029-2.5

12-Bit, 1MSPS, 16 Channels,

Single-Ended, Serial Interface ADC

been fully charged, there is no further input current. When

the converter goes into hold mode, the input impedance is

greater than 1GΩ.

Care must be taken regarding the absolute analog input

voltage. To maintain linearity of the converter, the CH0 -

CH15 and AINP inputs should be within the limits specified.

Outside of these ranges, converter linearity may not meet

specifications.