SG Micro SGM5200 Manual page 20

SGM5200
DETAILED DESCRIPTION (continued)
Table 1. Mode Control Register Settings for Manual Mode
Reset
Bits
State
DI[15:12] 0001
DI11 0
DI[10:7] 0000
DI6 0
DI5 0
DI4 0
DI[3:0] 0000
NOTE: 1. GPIO1 to GPIO3 are available only in TSSOP packaged device. TQFN device offers GPIO0 only.
Figure 7 shows an example in which manual mode is used
to scan channels 4, 7 and 9. The command to select
channel 4 (CH4) is issued in the n
corresponding to CH4 is available in the (n+2)
Internally, the SDI command is parsed and on the rising
edge of nCS of the (n+1)
nCS
SCLK
SDI
SDO
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Logic
State
0001 Selects manual mode.
1 Enables programming of bits DI[6:0].
0 Device retains values of DI[6:0] from the previous frame.
This 4-bit data represents the address of the next channel to be selected in the next frame.
DI10: MSB and DI7: LSB. For example, 0000 represents channel 0, 0001 represents channel 1 and so
forth.
0 Selects 0V to V
REF
1 Selects 0V to 2 × V
0 Device normal operation (no power-down).
1 Device powers down on the 16
SDO outputs current channel address of the channel on DO[15:12] followed by 12-bit conversion result
0
on DO[11:0].
GPIO3 - GPIO0 data (both input and output) is mapped onto DO[15:12] in the order shown below. Lower
data bits DO[11:0] represent 12-bit conversion result of the current channel.
1
DO15
(1)
GPIO3
GPIO data for the channels configured as output. Device will ignore the data for the channel which is
configured as input. SDI bit and corresponding GPIO information is given below.
DI3
(1)
GPIO3
th
frame and the data
th
frame and the MUX switches
Sample
CHx
Select CH4
Data CHx
Frame n
Figure 7. Example Manual Mode Timing Diagram
Single-Ended, Serial Interface ADC
input range (Range 1).
input range (Range 2).
REF
th
SCLK falling edge.
DO14
(1)
GPIO2
DI2
(1)
GPIO2
accordingly on the 2
On the rising edge of nCS of the (n+2)
signal for CH4 is sampled and the ADC sends the
th
frame. conversion data in this third frame. The device follows the
same steps and the ADC sends the conversion data for
CH7 and CH9 in the subsequent two frames.
Sample
CHy
t
CYCLE
Select CH7
Data CHy
Frame (n+1)
12-Bit, 1MSPS, 16 Channels,
Function
DO13
(1)
GPIO1
DI1
(1)
GPIO1
nd
falling edge of SCLK in this frame.
Sample
CH4
Select CH9
Data CH4
Frame (n+2)
DO12
(1)
GPIO0
DI0
(1)
GPIO0
th
frame, the input
Sample
CH7
SEPTEMBER 2021
20