SG Micro SGM5200 Manual page 28

SGM5200
DETAILED DESCRIPTION (continued)
Table 9. GPIO Program Register Settings
Reset Logic
Bits
State State
DI[15:12] NA 0100
DI[11:10] 00 00
1
DI9 0
0
1
DI8 0
0
1
DI7 0
0
000
xx1
010
DI[6:4] 000
100
110
Note: The following settings are valid for GPIO which are not assigned a specific function through bits DI[8:4].
1
DI3 0
0
1
DI2 0
0
1
DI1 0
0
1
DI0 0
0
Alarm Thresholds for GPIO Pins
Each channel has two alarm program registers, one for
setting the high alarm threshold and the other for setting the
low alarm threshold. For ease of programming, two alarm
programming registers per channel, corresponding to four
consecutive channels, are assembled into one group (a
total eight registers). There are four such groups for the
16-channel device respectively. The grouping of the various
channels for each SGM5200 device is listed in Table 10.
The details regarding programming the alarm thresholds
are illustrated in the flowchart in Figure 15. Table 11 lists the
details regarding the alarm program register settings.
Each alarm group requires 9 nCS frames for programming
their respective alarm thresholds. In the first frame the
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Device selects GPIO program registers for programming.
Do not program these bits to any logic state other than '00'.
Device resets all registers in the next nCS frame to the reset state shown in the corresponding tables (it also
resets itself).
Device normal operation.
Device configures GPIO3 as the device power-down input.
GPIO3 remains general purpose I or O. Program 0 for TQFN packaged device.
Device configures GPIO2 as device range input.
GPIO2 remains general purpose I or O. Program 0 for TQFN packaged device.
GPIO1 and GPIO0 remain general purpose I or O. Valid setting for TQFN packaged device.
Device configures GPIO0 as 'high or low' alarm output. This is an active high output. GPIO1 remains general
purpose I or O. Valid setting for TQFN packaged device.
Device configures GPIO0 as high alarm output. This is an active high output. GPIO1 remains general
purpose I or O. Valid setting for TQFN packaged device.
Device configures GPIO1 as low alarm output. This is an active high output. GPIO0 remains general purpose
I or O. Setting not allowed for TQFN packaged device.
Device configures GPIO1 as low alarm output and GPIO0 as a high alarm output. These are active high
outputs. Setting not allowed for TQFN packaged device.
GPIO3 pin is configured as general purpose output. Program 1 for TQFN packaged device.
GPIO3 pin is configured as general purpose input. Setting not allowed for TQFN packaged device.
GPIO2 pin is configured as general purpose output. Program 1 for TQFN packaged device.
GPIO2 pin is configured as general purpose input. Setting not allowed for TQFN packaged device.
GPIO1 pin is configured as general purpose output. Program 1 for TQFN packaged device.
GPIO1 pin is configured as general purpose input. Setting not allowed for TQFN packaged device.
GPIO0 pin is configured as general purpose output. Valid setting for TQFN packaged device.
GPIO0 pin is configured as general purpose input. Valid setting for TQFN packaged device.
12-Bit, 1MSPS, 16 Channels,
Single-Ended, Serial Interface ADC
Function
device enters the programming sequence and in each
subsequent frame it programs one of the registers from the
group. The device offers a feature to program less than
eight registers in one programming sequence. The device
exits the alarm threshold programming sequence in the
next frame after it encounters the first exit alarm program bit
high.
Table 10. Grouping of Alarm Program Registers
Group NO.
0 High and low alarm for channel 0, 1, 2 and 3.
1 High and low alarm for channel 4, 5, 6 and 7.
2 High and low alarm for channel 8, 9, 10 and 11.
3 High and low alarm for channel 12, 13, 14 and 15.
Registers
SEPTEMBER 2021
28