NXP Semiconductors MIMXRT1060/4-EVK Manual
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NXP Semiconductors MIMXRT1060/4-EVK Manual

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Author: MCUXpresso IDE Team
Version: 1.0.2 1
st
March 2019
Using the MIMXRT1060/4-EVK with MCUXpresso IDE v10.3.x

Table of Contents

1 Overview.................................................................................................................................2
2 Read Me First..........................................................................................................................3
MIMXRT1060 EVK Information.............................................................................................3
Debug Capabilities.................................................................................................................3
Also supplied with this Document.........................................................................................4
3 Overview of Board features related to Debug.......................................................................5
4 On board Debug Probe...........................................................................................................7
LPC-Link2 mode.....................................................................................................................7
Permanently installing LPC-Link2 Firmware - LPCScrypt......................................................8
Debug Connection.................................................................................................................8
5 DAPLink Firmware version.....................................................................................................9
Updating the DAPLink frmware............................................................................................9
6 Memories.............................................................................................................................10
Memory atributes and Cache(s)e.........................................................................................11
7 Flash Drivers.........................................................................................................................13
8 New Project Creation...........................................................................................................14
9 Project Modifcations required to enable S O Trace.........................................................16
Modifcations to pinmumuc.c.................................................................................................16
Modifcations to clockmuconfg.c...........................................................................................16
Modifcations within main()e................................................................................................16
S O Features......................................................................................................................17
hy...............................................................................................................18
11 Project Debug.....................................................................................................................19
12 Resets.................................................................................................................................21
13 MIMXRT1064......................................................................................................................22
Additional Memories for iMXRT1064..................................................................................22
Project Confguration to Specify both Flash Devices..........................................................22
Mass Erasing the MIMXRT1064...........................................................................................23
Using an updated Flash Driver............................................................................................23
14 Troubleshooting.................................................................................................................24
Erasing the QSPI Flash.........................................................................................................24
Use of mumu FI()e.....................................................................................................................25
Debug performance and the Data Cache............................................................................26
© 2019 NXP Semiconductors. All right reserved
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Summary of Contents for NXP Semiconductors MIMXRT1060/4-EVK

  • Page 1: Table Of Contents

    Author: MCUXpresso IDE Team Version: 1.0.2 1 March 2019 Using the MIMXRT1060/4-EVK with MCUXpresso IDE v10.3.x Table of Contents 1 Overview..........................2 2 Read Me First..........................3 MIMXRT1060 EVK Information.....................3 Debug Capabilities.........................3 Also supplied with this Document..................4 3 Overview of Board features related to Debug...............5 4 On board Debug Probe......................7...

  • Page 2: Overview

    EVK-IMXRT1060 version ..0. For more information on using MCUXpresso IDEg please see the MCUXpresso IDE User Guide. Note: this is a guide only and not intended as a defnitve document. © 2019 NXP Semiconductors. All right reserved...

  • Page 3: Read Me First

    Debug Capabilites ETB based instruction trace is not supported by this MCU. Howeverg when used with LPC- Link2 frmware or an ecternal debug probeg S O debug trace features are available. © 2019 NXP Semiconductors. All right reserved...

  • Page 4: Also Supplied With This Document

    Also supplied with this Document An ecample MIMXRT1060 project demonstrating the enabling of S O Trace • Features An updated LinkServer Flash driver for the iMXRT1064 • © 2019 NXP Semiconductors. All right reserved...

  • Page 5: Overview Of Board Features Related To Debug

    7. S 7 - DIP switches to select boot options (see break out section for details)e. Note: at the time of writingg the MIMXRT1060-EVK boards ship with QSPI fash 8. Board printed table showing boot switch seings © 2019 NXP Semiconductors. All right reserved...
  • Page 6 FI ‘freeze’)e. An approcimate 5 seconds or more pressing causes a forced OFF – but the Power LED can remain lit! 10. Target USB – can also be used to provide power to the target – (see 2b)e © 2019 NXP Semiconductors. All right reserved...

  • Page 7: On Board Debug Probe

    In addition to improved debug performance (which includes approcimately 4c speed improvement for fash programming)eg S O trace features are also available. Typical fash programming speed for a small application – LPC-Link2 frmware: Flash Program Summary: 27128 bytes in 0.37 seconds (71.99 KB/sec) © 2019 NXP Semiconductors. All right reserved...

  • Page 8: Permanently Installing Lpc-Link2 Firmware - Lpcscrypt

    Note: if the board has been confgured correctly the LED nexft to J1 will light green. If the LED is not lit, the MCU will not be powered and debug will fail, resultng in an error similar to that below (despite the DAPLink debug connecton being available : © 2019 NXP Semiconductors. All right reserved...

  • Page 9: Daplink Firmware Version

    6. Open this drive and drag the previously downloaded frmware onto the fler window a. The fler window should close when the frmware update has completed 7. Eject the device 8. Power of the board © 2019 NXP Semiconductors. All right reserved...

  • Page 10: Memories

    SRAM_ITC at 0x0: This 128KB device (FlecRAM)e is on chip SRAMg and tightly coupled to the MCU and will 'seen' by the CPU before the cacheg therefore the contents of this RAM will © 2019 NXP Semiconductors. All right reserved...

  • Page 11: Memory Atributes And Cache(S)E

    It is strongly recommended that (if used) this funcpon is examined and understood to ensure the memory system is confgured as desired. Note: in SDK version 2.5.x the 32MB SDRAM region is confggree so the last 2MB will not be cachee: © 2019 NXP Semiconductors. All right reserved...
  • Page 12 Warning: It has been observed that placing stack memory within this uncached region at the end of SDRAM can result in loss of debug control. See Troubleshoopng secpon to recover debug control. © 2019 NXP Semiconductors. All right reserved...

  • Page 13: Flash Drivers

    MIMXRT1060_SFDP_HYPERFLASH.cfx. This driver can be used for RT1060 board designs that use Hyperfash rather than QSPI. Please see the MCUXpresso IDE v10.3 User Guide 15.2.4 “Flash Drivers using SFDP protocol”) for more information. © 2019 NXP Semiconductors. All right reserved...

  • Page 14: New Project Creation

    1 – To create a New Projectg Click 'New Project' to launch the New Project izard: 2 - Ensure the EVK board is selected (otherwise board features including fash memory will not be available)e: 3 - Click Nect (accepting all the default options)e: © 2019 NXP Semiconductors. All right reserved...
  • Page 15 RAM region (SRAMmuDTC)e for stack and global data. This RAM region is used because the SRAMmuDTC is marked by the SDK as the frst RAM region for new projects (this selected RAM can of course be changed)e. © 2019 NXP Semiconductors. All right reserved...

  • Page 16: Project Modifcations Required To Enable S O Trace

    /* Set Trace clock source. */ CLOCK_SetMux(kCLOCK_TraceMux, 3); /* make this edit */ Modifcatons within main()s Afer the function BOARD_BootClockRUNg add the lines: *((uint32_t *)(0x400E0600)) = (1 << 11); /* enable TPIU clock */ CLOCK_EnableClock(kCLOCK_Trace); © 2019 NXP Semiconductors. All right reserved...

  • Page 17: S O Features

    Please refer to the MCUXpresso IDE S O Trace Guide for information on the use of S O trace features. © 2019 NXP Semiconductors. All right reserved...

  • Page 18: Xip How And Hy

    Note: this image header will only be created if the image is linked to the start of Flash at 0xf60000000 (the New Project default . © 2019 NXP Semiconductors. All right reserved...

  • Page 19: Project Debug

    Probe(0): Connected&Reset. DpID: 0BD11477. CpuID: 00000C27. Info: <None> Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled. Content of CoreSight Debug ROM(s): RBASE E00FD000: CID B105100D PID 000008E88C ROM (type 0x1) ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM (type 0x1) © 2019 NXP Semiconductors. All right reserved...
  • Page 20 Starting execution using system reset and halt target Note - system reset leaves VTOR at 0x200000 (not 0x60000000 which a booted image might assume) Stopped (Was Reset) [Reset from Unknown] Stopped: Breakpoint #1 © 2019 NXP Semiconductors. All right reserved...

  • Page 21: Resets

    The exfpected result can be achieved by using the QuickStart ‘Terminate, Build and Debug7 feature. All informaton will of course be lost if the target board is power cycled. © 2019 NXP Semiconductors. All right reserved...

  • Page 22: Mimxrt1064

    A project memory confguration to specify both fash devices will look similar to the image below – where you can see additional lines have been added to reference the board fash (blue)e and the appropriate board fashdriver (red)e. © 2019 NXP Semiconductors. All right reserved...

  • Page 23: Mass Erasing The Mimxrt1064

    Then locate the fash driver via the Browse Project option shown below. This option also provides benefts if the project is shared with others since the updated fash driver will ‘travel’ with the shared project. © 2019 NXP Semiconductors. All right reserved...

  • Page 24: Erasing The Qspi Flash

    GUI Flash Tool icon (the chip)e: 5. Select the probe as for a normal debug operationg then ensure the 'Erase fash memory' tab is selected. Click the 'Mass erase' radio buton and then click OK. © 2019 NXP Semiconductors. All right reserved...

  • Page 25: Use Of Mumu Fi()E

    Note: the supplied ecample project demonstrates the use of this feature. At the time of writingg no SDK ecamples for this MCU perform a mumu FI()e call that can occur directly afer reset and hence avoid this problem. © 2019 NXP Semiconductors. All right reserved...

  • Page 26: Debug Performance And The Data Cache

    However there will be a debug performance penalty when this module is used. Note: this module is not required if the SDRAM (or OC_RAM only contains constant or uncached data. © 2019 NXP Semiconductors. All right reserved...

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