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RXB4N
RXB4P
RXB3N
RXB3P
RXBCLKN
RXBCLKP
RXB2N
RXB2P
RXB1N
RXB1P
RXB0N
RXB0P
RXA4N
RXA4P
RXA3N
RXA3P
RXACLKN
RXACLKP
RXA2N
RXA2P
RXA1N
RXA1P
RXA0N
RXA0P
L/DIM0_VS
L/DIM0_VS
L/DIM0_SCLK
L/DIM0_SCLK
L/DIM0_MOSI
L/DIM0_MOSI
C103
33pF
50V
OPT
UART_RX
UART_TX
SPI_SCLK
+3.3V
SPI_CS
SPI_DI
SPI_DO
R111
R112
+3.3V
1K
1K
I2C_BE_SDA1
I2C_BE_SCL1
+3.3V
TRST_N
R186
SW100
3.3K
OPT
JTP-1127WEM
LG1122_RST
R133
0
RESET Input
1) LG1122_RST
: From Main SOC
SPI_DL_MODE
2) HW_RESET
: From
HW Switch
XTAL_OUT
3) SPI_DL_MODE : Download Mode to Flash Mem
XTAL_IN
FPGA_LVDS_INFO
GPIO[1:0]
: Local Dimming Debugging
GPIO[7:3] = PWM[4:0]
FRAME_OPT
1) GPIO[3] : 120Hz Mode --> 60 or 120Hz (Programmable)
240Hz Mode --> 120 or 240Hz (Programmable)
TCON_OPT
SOC_OPT
2) GPIO[4] : 120Hz Mode --> 60 or 120Hz (Programmable)
REVERSE_OPT
240Hz Mode --> 120 or 240Hz (Programmable)
DISPLAY_OPT
3) GPIO[5] : 120Hz Mode --> 120 or 240Hz (Programmable)
240Hz Mode --> 240 or 480Hz (Programmable)
4) GPIO[6] : 120Hz Mode --> 120Hz (Fixed)
240Hz Mode --> 240Hz (Fixed)
5) GPIO[7] : 120Hz Mode --> 120Hz (Fixed)
240Hz Mode --> 240Hz (Fixed)
GPIO[8]
: External Vsync input for Local Dimming block
GPIO[10]
: T-Con L/R Sync Monitor(AR)
GPIO[12:11]
: S/W I2C_Master CH
GPIO[26:16]
: BLU Direct Control CH
+3.3V
GPIO[28:27]
: I2C for PQ tunning
R119
10K
R107
10K
GPIO NO
11
12
13
14
15
20
21
22
XTAL(24.75MHz)
R106
1M
X100
24.75MHz
X-TAL_1
GND_2
XTAL_IN
1
4
GND_1
X-TAL_2
2
3
C100
C104
27pF
27pF
50V
50V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
IC100
LG1123
AC1
B2
RXA0P
TX0P
AC2
A2
RXA0N
TX0N
AB3
A3
RXA1P
TX1P
AC3
B3
RXA1N
TX1N
AB2
C4
RXA2P
TX2P
AB1
C3
RXA2N
TX2N
AA1
B4
RXACLKP
TX3P
AA2
A4
RXACLKN
TX3N
Y3
A5
RXA3P
TX4P
AA3
B5
RXA3N
TX4N
Y2
C6
RXA4P
TX5P
Y1
C5
RXA4N
TX5N
B6
TX6P
W1
A6
RXB0P
TX6N
W2
A7
RXB0N
TX7P
V3
B7
RXB1P
TX7N
W3
RXB1N
V2
A23
RXB2P
TXA0P
TXC0P
V1
B23
RXB2N
TXA0N
TXC0N
U1
C22
RXBCLKP
TXA1P
TXC1P
U2
C23
RXBCLKN
TXA1N
TXC1N
T3
B22
RXB3P
TXA2P
TXC2P
U3
A22
RXB3N
TXA2N
TXC2N
T2
A21
RXB4P
TXACLKP
TXCCLKP
T1
B21
RXB4N
TXACLKN
TXCCLKN
C20
TXA3P
TXC3P
R148
33 OPT
B26
C21
L_VSOUT_LD
TXA3N
TXC3N
E2
B20
R149
33
R_VSOUT_LD
TXA4P
TXC4P
33 OPT
C26
A20
R150
M0_SCLK
TXA4N
TXC4N
33 OPT
E22
R151
M0_MOSI
D24
A19
M1_SCLK
TXB0P
TXD0P
G22
B19
M1_MOSI
TXB0N
TXD0N
D2
C18
R152
33
M2_SCLK
TXB1P
TXD1P
E1
C19
R153
33
M2_MOSI
TXB1N
TXD1N
C105
C107
D1
B18
M3_SCLK
TXB2P
TXD2P
33pF
33pF
D3
A18
50V
50V
M3_MOSI
TXB2N
TXD2N
OPT
OPT
A17
TXBCLKP
TXDCLKP
G3
B17
UART_RXD
TXBCLKN
TXDCLKN
H3
C16
R124
33
UART_TXD
TXB3P
TXD3P
C17
TXB3N
TXD3N
G1
B16
R125
33
SPI_SCLK
TXB4P
TXD4P
G2
A16
R126
33
SPI_CS
TXB4N
TXD4N
F2
SPI_DI
F1
A15
R127
33
SPI_DO
TXC0P
TXA0P
B15
TXC0N
TXA0N
J1
C14
R128
0
SDA_M
TXC1P
TXA1P
J2
R129
0
C15
SCL_M
TXC1N
TXA1N
R130
0
H1
B14
SDA_S
TXC2P
TXA2P
R131
0
H2
A14
SCL_S
TXC2N
TXA2N
A13
TXCCLKP
TXACLKP
K2
B13
R101
10K
SMODE
TXCCLKN
TXACLKN
J3
C12
TMODE0
TXC3P
TXA3P
K3
C13
TMODE1
TXC3N
TXA3N
L3
B12
TMODE2
TXC4P
TXA4P
M3
A12
TMODE3
TXC4N
TXA4N
M2
A11
TRST_N
TXD0P
TXB0P
L1
B11
R132
33
TDO
TDO
TXD0N
TXB0N
L2
C10
TDI
TDI
TXD1P
TXB1P
M1
C11
TCK
TCLK
TXD1N
TXB1N
N1
B10
TMS
TMS
TXD2P
TXB2P
A10
TXD2N
TXB2N
K1
A9
R134
0
PORES_N
TXDCLKP
TXBCLKP
B9
R135
0
TXDCLKN
TXBCLKN
AF6
C8
XTALO
TXD3P
TXB3P
AE6
C9
XTALI
TXD3N
TXB3N
B8
TXD4P
TXB4P
N2
A8
R136
33 OPT
MON_SYNC0
TXD4N
TXB4N
N3
R137
33 OPT
MON_SYNC1
R138
33 OPT
P3
C25
MON_INTR
GPIO[16]
C24
GPIO[17]
33
R162
C1
AD1
3D_EN
VIREF_REXT
GPIO[18]
R1
33
R161
GPIO[19]
C2
R2
R167
TX_LOCKN
GPIO[20]
L/DIMMING_OPT
47K
R3
R140
GPIO[21]
OPT_READY_1
+3.3V
33 OPT
AB5
P1
GPIO[0]
GPIO[22]
OPT_READY_2
33 OPT
AB4
A25
R141
GPIO[1]
GPIO[23]
OPT_7
33 OPT
AD5
D23
R142
GPIO[2]
GPIO[24]
AC5
D22
R143
33 OPT
R172
R173
GPIO[3]
GPIO[25]
AE4
F22
R144
33 OPT
4.7K
4.7K
GPIO[4]
GPIO[26]
R195
33 OPT
AD4
E23
R164
33
GPIO[5]
GPIO[27]
I2C_SCL_PQ
R146
33
AC4
E3
R165
33
GPIO[6]
GPIO[28]
I2C_SDA_PQ
R196
33 OPT
AF3
F3
R156
33
OPT
FLASH_WP
GPIO[7]
GPIO[29]
33 OPT
AE3
A24
R197
R113
33
TCON_I2C_EN
GPIO[8]
GPIO[30]
33 OPT
AD3
P2
R198
GPIO[9]
GPIO[31]
R139
33 OPT
AF2
R199
GPIO[10]
10K
AE2
GPIO[11]
AD2
GPIO[12]
AE1
GPIO[13]
B25
GPIO[14]
B24
GPIO[15]
I2C Slave Address
0x1C (Direct access)
0xB2 (In-direct access)
+3.3V
+3.3V
+3.3V
+3.3V
R108
R147
R168
R170
10K
10K
10K
10K
240Hz
OLED
W/O_TCON
MTK
IMAGE_NORMAL
FRAME_OPT
TCON_OPT
SOC_OPT
REVERSE_OPT
R116
R145
R169
R171
10K
10K
10K
10K
LCD
120Hz
W_TCON
L9(LG1152)
IMAGE_REVERSE
READY FOR H/W OPTION
OPTION NAME
HIGH
LOW
FRAME_OPT
240Hz
120Hz
+3.3V
+3.3V
JIG_OPT
Without_TCON
With_TCON
R189
R191
(for FRC3 JIG)
10K
10K
L/D_ON_FRC
SOC_OPT
L9 (LG1152)
MTK
OPT
L/DIMMING_OPT
OPT_READY_1
IMAGE_OPT
IMAGE_NORMAL
IMAGE_OPT
R190
R192
(for 72INCH)
(for NON_72INCH)
10K
10K
L/D_ON_MAIN
DISPLAY_OPT
OLED
LCD
L/DIMMING_OPT
L/D_ON_FRC
L/D_ON_MAIN
OPT_READY_1
OPT
Default
OPT_READY_2
OPT
Default
SPI FLASH(4MByte)
IC101
MX25L3206EM2I-12G
R157
R158
4.7K
10K
XTAL_OUT
OPT
CS#
VCC
1
8
SPI_CS
R159
SO/SIO1
HOLD#
2
7
SPI_DI
33
R160
WP#
SCLK
0
FLASH_WP
3
6
R185
10K
GND
SI/SIO0
OPT
4
5
Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
IC100
LG1123
B1
P10
VSS_1
VSS_135
C7
P11
VSS_2
VSS_136
D4
P12
VSS_3
VSS_137
D5
P13
VSS_4
VSS_138
D6
P14
VSS_5
VSS_139
D7
P15
VSS_6
VSS_140
D8
P16
VSS_7
VSS_141
D18
P17
VSS_8
VSS_142
D19
P19
VSS_9
VSS_143
D20
P21
VSS_10
VSS_144
D21
P22
VSS_11
VSS_145
D25
P24
VSS_12
VSS_146
D26
R4
VSS_13
VSS_147
E4
R5
VSS_14
VSS_148
E5
R6
VSS_15
VSS_149
E6
R8
VSS_16
VSS_150
E7
R10
VSS_17
VSS_151
E8
R11
VSS_18
VSS_152
E9
R12
VSS_19
VSS_153
E10
R13
VSS_20
VSS_154
E11
R14
VSS_21
VSS_155
E12
R15
VSS_22
VSS_156
E13
R16
VSS_23
VSS_157
E14
R17
VSS_24
VSS_158
E15
R19
VSS_25
VSS_159
E16
R21
VSS_26
VSS_160
E17
R22
VSS_27
VSS_161
E18
T5
VSS_28
VSS_162
E19
T6
VSS_29
VSS_163
E21
T8
VSS_30
VSS_164
E24
T10
VSS_31
VSS_165
F5
T11
VSS_32
VSS_166
F7
T12
VSS_33
VSS_167
F8
T13
VSS_34
VSS_168
F9
T14
VSS_35
VSS_169
F10
T15
VSS_36
VSS_170
F11
T16
VSS_37
VSS_171
F12
T17
VSS_38
VSS_172
F13
T19
VSS_39
VSS_173
F14
T21
VSS_40
VSS_174
F15
T22
VSS_41
VSS_175
F16
U5
VSS_42
VSS_176
F17
U6
VSS_43
VSS_177
F18
U8
VSS_44
VSS_178
F19
U10
VSS_45
VSS_179
F21
U11
VSS_46
VSS_180
F23
U12
VSS_47
VSS_181
G5
U13
VSS_48
VSS_182
G21
U14
VSS_49
VSS_183
G23
U15
VSS_50
VSS_184
H5
U16
VSS_51
VSS_185
H8
U17
VSS_52
VSS_186
H9
U19
VSS_53
VSS_187
H10
U21
VSS_54
VSS_188
H11
U22
VSS_55
VSS_189
H12
V5
VSS_56
VSS_190
H13
V6
VSS_57
VSS_191
H14
V8
VSS_58
VSS_192
H15
V19
VSS_59
VSS_193
H16
V21
VSS_60
VSS_194
H17
V22
VSS_61
VSS_195
H18
W5
VSS_62
VSS_196
H19
W6
VSS_63
VSS_197
H21
W8
VSS_64
VSS_198
H22
W9
VSS_65
VSS_199
H23
W10
VSS_66
VSS_200
J5
W11
VSS_67
VSS_201
J8
W12
VSS_68
VSS_202
J19
W13
VSS_69
VSS_203
J21
W14
VSS_70
VSS_204
J22
W15
VSS_71
VSS_205
K4
W16
VSS_72
VSS_206
K5
W17
VSS_73
VSS_207
K8
W18
VSS_74
VSS_208
K10
W19
VSS_75
VSS_209
3D_EN
K11
W21
VSS_76
VSS_210
K12
W22
VSS_77
VSS_211
TCON_I2C_EN
K13
Y4
VSS_78
VSS_212
K14
Y5
VSS_79
VSS_213
OPT_7
K15
Y21
VSS_80
VSS_214
K16
Y22
VSS_81
VSS_215
K17
AA4
VSS_82
VSS_216
K19
AA7
VSS_83
VSS_217
K21
AA8
VSS_84
VSS_218
K22
AA9
VSS_85
VSS_219
L4
AA10
VSS_86
VSS_220
L5
AA11
VSS_87
VSS_221
L8
AA12
VSS_88
VSS_222
L10
AA13
VSS_89
VSS_223
L11
AA14
VSS_90
VSS_224
L12
AA15
VSS_91
VSS_225
L13
AA16
VSS_92
VSS_226
L14
AA17
VSS_93
VSS_227
L15
AA18
VSS_94
VSS_228
L16
AA19
VSS_95
VSS_229
L17
AA20
VSS_96
VSS_230
L19
AA21
VSS_97
VSS_231
L21
AA22
VSS_98
VSS_232
L22
AA23
VSS_99
VSS_233
M4
AB6
VSS_100
VSS_234
M5
AB7
VSS_101
VSS_235
M6
AB8
VSS_102
VSS_236
M8
AB9
VSS_103
VSS_237
M10
AB10
VSS_104
VSS_238
M11
AB11
VSS_105
VSS_239
M12
AB12
VSS_106
VSS_240
M13
AB13
VSS_107
VSS_241
M14
AB14
VSS_108
VSS_242
M15
AB15
VSS_109
VSS_243
M16
AB16
VSS_110
VSS_244
M17
AB17
VSS_111
VSS_245
M19
AB18
VSS_112
VSS_246
M21
AB19
VSS_113
VSS_247
DISPLAY_OPT
M22
AB20
VSS_114
VSS_248
N4
AB21
VSS_115
VSS_249
N5
AB22
VSS_116
VSS_250
N6
AB23
VSS_117
VSS_251
N8
AC6
VSS_118
VSS_252
N10
AC7
VSS_119
VSS_253
N11
AC8
VSS_120
VSS_254
N12
AC9
VSS_121
VSS_255
N13
AC10
VSS_122
VSS_256
N14
AC23
VSS_123
VSS_257
N15
AC24
VSS_124
VSS_258
N16
AC25
VSS_125
VSS_259
N17
AC26
VSS_126
VSS_260
N19
AD6
VSS_127
VSS_261
+3.3V
N21
AD7
VSS_128
VSS_262
N22
AD8
VSS_129
VSS_263
N24
AD17
R193
VSS_130
VSS_264
P4
AD18
10K
VSS_131
VSS_265
P5
AE8
OPT
VSS_132
VSS_266
P6
AF4
VSS_133
VSS_267
OPT_READY_2
P8
AF8
VSS_134
VSS_268
R194
10K
+3.3V
C124
0.1uF
R174
3.3K
SPI_SCLK
SPI_DO
All of OPT decaps must be placed on PCB Bottom side
IC100
LG1123
+0.9VDC
+3.3V_IO
J9
F6
VDD_1
VDD33_1
J10
F20
VDD_2
VDD33_2
J11
G6
VDD_3
VDD33_3
+1.8V Power Separation
J16
H6
VDD_4
VDD33_4
J17
J6
VDD_5
VDD33_5
+1.8V
J18
K6
VDD_6
VDD33_6
K9
L6
VDD_7
VDD33_7
K18
Y6
VDD_8
VDD33_8
L9
AA6
VDD_9
VDD33_9
+1.8V
L18
VDD_10
M9
E20
VDD_11
VDD18_1
M18
F4
VDD_12
VDD18_2
N9
G4
VDD_13
VDD18_3
N18
H4
VDD_14
VDD18_4
P9
J4
VDD_15
VDD18_5
P18
AA5
VDD_16
VDD18_6
+1.8LVDS_RX
R9
VDD_17
R18
T4
VDD_18
LVRX_VDD18_1
T9
U4
VDD_19
LVRX_VDD18_2
T18
V4
VDD_20
LVRX_VDD18_3
U9
W4
+1.8V
VDD_21
LVRX_VDD18_4
+1.8LVDS_TX
U18
VDD_22
V9
D9
VDD_23
LVTX_VDD18_1
V10
D10
VDD_24
LVTX_VDD18_2
V11
D11
VDD_25
LVTX_VDD18_3
V12
D12
VDD_26
LVTX_VDD18_4
V13
D13
VDD_27
LVTX_VDD18_5
V14
D14
VDD_28
LVTX_VDD18_6
V15
D15
VDD_29
LVTX_VDD18_7
V16
D16
VDD_30
LVTX_VDD18_8
V17
D17
VDD_31
LVTX_VDD18_9
V18
+0.9VDC
VDD_32
J12
LVTX_VDD_1
J13
LVTX_VDD_2
J14
LVTX_VDD_3
+1.8V
J15
LVTX_VDD_4
+0.9AVDD
AE7
AVDD09_1
AF7
AVDD09_2
+1.8V_AVDD
AE5
AVDD18_1
AF5
AVDD18_2
+3.3V_IO Decaps
+3.3V_IO
+3.3V Power Separation
+3.3V
+0.9VDC Decaps
+0.9VDC
+0.9V Power Separation
+0.9V
SPI/I2C For Aardvak Interface
For JTAG Interface
+3.3V
+3.3V
P100
P101
12507WR-10L
12507WR-08L
R175
1K
C125
0.1uF
1
1
OPT
16V
2
2
R180
33
SPI_CS
TDI
3
SPI_DO
3
R181
33
TMS
4
4
R182
33
SPI_SCLK
TCK
5
5
SPI_DI
TDO
R183
33
6
6
SPI_DL_MODE
TRST_N
OPT
7
R176
0
7
R177
0
8
FLASH_WP
8
OPT
R178
0
9
9
I2C_BE_SDA1
R179
0
10
I2C_BE_SCL1
11
+1.8VLVDS_RX Decaps
+1.8LVDS_RX
+1.8LVDS_RX
L100
MLB-201209-0120P-N2
C149
C161
C126
C134
0.1uF
0.1uF
4.7uF
4.7uF
16V
16V
10V
10V
+1.8VLVDS_TX Decaps
+1.8LVDS_TX
+1.8LVDS_TX
L101
MLB-201209-0120P-N2
C162
C127
C135
0.1uF
4.7uF
4.7uF
16V
10V
10V
+1.8V_AVDD
+1.8V_AVDD
L104
MLB-201209-0120P-N2
C142
C152
C158
4.7uF
4.7uF
0.1uF
10V
10V
16V
C151
C157
10uF
10uF
25V
25V
+3.3V_IO
L102
MLB-201209-0120P-N2
C129
C137
4.7uF
4.7uF
10V
10V
C148
C154
10uF
10uF
25V
25V
+0.9AVDD Decaps
+0.9AVDD
+0.9VDC
+0.9VDC
+0.9AVDD
L103
L105
MLB-201209-0120P-N2
MLB-201209-0120P-N2
C131
C139
C144
C153
C159
C163
4.7uF
4.7uF
4.7uF
4.7uF
0.1uF
0.1uF
10V
10V
10V
10V
16V
16V
UART For CPU
I2C For PQ tunning
P103
P102
12507WR-04L
12507WR-04L
+3.3V
1
OPT
1
R184
3.3K
2
2
UART_RX
3
3
I2C_SDA_PQ
4
I2C_SCL_PQ
4
UART_TX
5
5
120Hz Back-End Board
2011. 07. 05
FRC-III(LG1122)
1
6
LGE Internal Use Only
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