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Send these LVDS
signals to
FPGA
+3.3V_SERDES
LD 5002 : GPIO1 default value
is power on reset status.
VDD33_1
1
NC_1
2
THERMAL
GPIO0
3
49
GPIO1
2.2K
4
IC5002
R5006
DC_B
5
RS
DS32EL0124
6
VDD25_1
+2.5V_SERDES
7
NC_2
8
OPT
C5067
NC_3
9
22uF
10V
NC_4
10
GPIO2
11
NC_5
12
+3.3V_SERDES
0.1uF
C5008
C5006
0.1uF
R5048
30
1%
0.1uF close
to pin15,18
C5074
R5055
30
1%
C5083
+3.3V_SERDES
VDD33_1
1
NC_1
2
THERMAL
GPIO0
3
49
GPIO1
2.2K
4
IC5001
R5005
DC_B
5
RS
DS32EL0124
6
VDD25_1
+2.5V_SERDES
7
NC_2
8
OPT
C5068
NC_3
9
22uF
10V
NC_4
10
GPIO2
11
NC_5
12
+3.3V_SERDES
30
R5049
1%
C5007
0.1uF
C5075
30
R5056
1%
C5076
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3V_SERDES
+2.5V_SERDES
+3.3V_SERDES
VDD33_4
36
VDD25_3
35
SMB_CS
34
FPGA_LINK3B_SMB_CS
SCK
33
FPGA_B_SCK
SDA
32
FPGA_B_SDA
0 OPT
R5016
LOCK
0
R5011
31
LINK3B_LOCK_N
OPTIC_SERDES_RESET
RESET
30
NC_14
29
VDDPLL
28
LF_CP
27
R5012 0
0.033uF
+2.5V_SERDES
C5026
22uF and 0.1uF
LF_REF
22uF
26
C5013
close to pin25
10V
VDD25_2
25
R5012,C5013 CLOSER TO IC5002
0.1uF close
to pin25.
LINK3B_RXIN_N
+3.3V_SERDES
VDD33_1
LINK3B_RXIN_P
NC_1
GPIO0
GPIO1
2.2K
R5023
DC_B
VDD25_1
+2.5V_SERDES
NC_2
OPT
C5070
NC_3
22uF
10V
NC_4
GPIO2
NC_5
+3.3V_SERDES
+3.3V_SERDES
+2.5V_SERDES
+3.3V_SERDES
VDD33_4
36
VDD25_3
35
SMB_CS
34
FPGA_LINK4B_SMB_CS
SCK
33
FPGA_B_SCK
SDA
32
FPGA_B_SDA
0 OPT
R5015
LOCK
R5010
31
0
LINK4B_LOCK_N
OPTIC_SERDES_RESET
RESET
30
NC_14
29
VDDPLL
28
LF_CP
0
27
+2.5V_SERDES
0.033uF
C5025
R5009
LF_REF
26
C5014
22uF
10V
VDD25_2
25
C5019 CLOSER TO IC5001
LINK4B_RXIN_N
LINK4B_RXIN_P
+3.3V_SERDES
FPGA_B_SCK
FPGA_B_SDA
C5022
C5021
5pF
5pF
50V
50V
+3.3V_SERDES
+3.3V_SERDES
+2.5V_SERDES
VDD33_4
1
36
VDD25_3
2
35
THERMAL
SMB_CS
3
49
34
FPGA_LINK1B_SMB_CS
SCK
4
33
IC5003
FPGA_B_SCK
SDA
5
32
FPGA_B_SDA
RS
DS32EL0124
LOCK
R5026
0
6
31
LINK1B_LOCK_N
RESET
7
30
NC_14
8
29
VDDPLL
9
28
LF_CP
0
10
27
+2.5V_SERDES
0.033uF
R5025
LF_REF
11
26
C5033
VDD25_2
12
25
C5033 CLOSER TO IC5003
C5030
0.1uF
R5053
30
1%
LINK1B_RXIN_N
C5077
R5057
30
1%
LINK1B_RXIN_P
C5078
+2.5V_NORMAL
+2.5V_SERDES
L5005
C5063
C5064
C5073
0.1uF
10uF
22uF
16V
25V
10V
+3.3V_NORMAL
+3.3V_SERDES
OPT
L5004
C5065
C5066
C5072
0.1uF
10uF
22uF
10V
16V
25V
VDD33_1
VDD33_4
1
36
NC_1
VDD25_3
2
35
THERMAL
GPIO0
SMB_CS
3
49
34
GPIO1
SCK
2.2K
4
33
IC5004
R5031
DC_B
SDA
5
32
RS
DS32EL0124
LOCK
6
31
VDD25_1
RESET
+2.5V_SERDES
7
30
NC_2
NC_14
OPT
8
29
C5071
NC_3
VDDPLL
22uF
9
28
10V
NC_4
LF_CP
10
27
GPIO2
LF_REF
11
26
NC_5
VDD25_2
12
25
+3.3V_SERDES
C5044
0.1uF
R5052
30
1%
C5079
R5051
30
1%
+3.3V_SERDES
C5082
0 OPT
R5034
OPTIC_SERDES_RESET
C5043
22uF
10V
+3.3V_SERDES
VDD33_1
1
36
NC_1
2
35
THERMAL
GPIO0
3
49
34
GPIO1
2.2K
4
33
IC5005
R5032
DC_B
5
32
RS
DS32EL0124
6
31
VDD25_1
+2.5V_SERDES
7
30
NC_2
8
29
OPT
C5069
NC_3
9
28
22uF
10V
NC_4
10
27
GPIO2
11
26
NC_5
12
25
+3.3V_SERDES
R5050
30
C5046
1%
0.1uF
C5080
R5054
30
1%
C5081
LG1152 A0
Interface block
+3.3V_SERDES
+2.5V_SERDES
+3.3V_SERDES
FPGA_LINK5B_SMB_CS
FPGA_B_SCK
FPGA_B_SDA
0 OPT
R5043
R5039
0
LINK5B_LOCK_N
OPTIC_SERDES_RESET
0
+2.5V_SERDES
0.033uF
C5060
R5038
C5051
22uF
10V
C5056 CLOSER TO IC5004
LINK5B_RXIN_N
LINK5B_RXIN_P
+3.3V_SERDES
+2.5V_SERDES
+3.3V_SERDES
VDD33_4
VDD25_3
SMB_CS
FPGA_LINK2B_SMB_CS
SCK
FPGA_B_SCK
SDA
FPGA_B_SDA
0 OPT
R5045
LOCK
R5041
0
LINK2B_LOCK_N
OPTIC_SERDES_RESET
RESET
NC_14
VDDPLL
LF_CP
0
+2.5V_SERDES
0.033uF
C5062
R5040
LF_REF
C5053
22uF
10V
VDD25_2
C5053 CLOSER TO IC5005
LINK2B_RXIN_N
LINK2B_RXIN_P
72
100
LGE Internal Use Only
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