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/RESET2V5
R3108
OPT
Mode Pins --> determine configuration mode
Parallel configuration mode bus is auto-detected by the configuration logic.
M[1:0] = 10
CCLK Direction : Input
Bus Width : 8, 16
+2.5V_FPGA
OPT
FPGA_SPI_DI
FPGA_SPI_CZ
FPGA_SPI_CLK
FPGA_SPI_DO
+2.5V_FPGA
R3105
10K
OPT
+2.5V_NORMAL
L3103
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+2.5V_FPGA
XC6SLX16-3CSG324I
From DES IC to FPGA
R3110
4.7K
C3114
R3
0.1uF
BACK_CHANNEL_N
IO_L62P_D5_2
U3
IO_L65P_INIT_B_2
T4
FPGA_LINK5B_RXOUT4_P
IO_L63P_2
U5
FPGA_LINK5B_RXOUT3_P
IO_L49P_D3_2
T5
IO_L48N_RDWR_B_VREF_2
V7
FPGA_LINK5B_RXOUT1_N
IO_L43N_2
U7
FPGA_LINK5B_RXOUT1_P
IO_L43P_2
T7
IO_L46N_2
V8
FPGA_LINK5B_RXOUT0_N
IO_L41N_VREF_2
U8
FPGA_LINK5B_RXOUT0_P
IO_L41P_2
T8
FPGA_LINK5B_RXCLKOUT_N
IO_L31N_GCLK30_D15_2
V10
IO_L30N_GCLK0_USERCCLK_2
U10
IO_L30P_GCLK1_D13_2
T10
FPGA_LINK2B_RXCLKOUT_N
IO_L29N_GCLK2_2
U11
FPGA_LINK2B_RXOUT4_P
IO_L23P_2
T11
IO_L16N_VREF_2
V13
FPGA_LINK2B_RXOUT2_N
IO_L14N_D12_2
U13
FPGA_LINK2B_RXOUT2_P
IO_L14P_D11_2
T13
IO_L3N_MOSI_CSI_B_MISO0_2
V14
FPGA_LINK2B_RXOUT1_N
IO_L12N_D2_MISO3_2
T14
FPGA_LINK2B_RXOUT1_P
IO_L12P_D1_MISO2_2
T15
IO_L1N_M0_CMPMISO_2
V16
IO_L2N_CMPMOSI_2
U16
IO_L2P_CMPCLK_2
V6
FPGA_LINK5B_RXOUT2_N
IO_L45N_2
0
R3111
V3
IO_L65N_CSO_B_2
V4
FPGA_LINK5B_RXOUT4_N
IO_L63N_2
V5
FPGA_LINK5B_RXOUT3_N
IO_L49N_D4_2
V9
VCXO1_CLK_Y
IO_L32N_GCLK28_2
T6
FPGA_LINK5B_RXOUT2_P
IO_L45P_2
V11
FPGA_LINK2B_RXOUT4_N
IO_L23N_2
0.1uF
C3115
T3
IO_L62N_D6_2
BACK_CHANNEL_P
R15
IO_L1P_CCLK_2
22
R3132
R13
IO_L3P_D0_DIN_MISO_MISO1_2
22
R3109
N12
IO_L13P_M1_2
P12
VCXO1_CTRL
IO_L13N_D10_2
R11
IO_L16P_2
R10
FPGA_LINK2B_RXCLKOUT_P
IO_L29P_GCLK3_2
R8
FPGA_LINK5B_RXCLKOUT_P
IO_L31P_GCLK31_D14_2
T9
IO_L32P_GCLK29_2
R7
IO_L46P_2
R5
IO_L48P_D7_2
N5
LINK3B_LOCK_N
IO_L64P_D8_2
P6
IO_L64N_D9_2
+2.5V_VCXO
R5421
10K
VCXO1_CTRL
C3116
2200pF
50V
+2.5V_FPGA
+3.3V_FPGA
IC2001
P9
VCCO_2_1
R12
VCCO_2_3
R6
VCCO_2_2
U14
VCCO_2_6
U4
VCCO_2_4
U9
VCCO_2_5
+2.5V_FPGA
4.7uF
0.47uF
0.47uF
10uF
C3106
0.47uF
10V
16V
16V
16V
25V
C3102
C3103
C3104
C3105
Decouplingcapacitors forVCCO Bank2
+2.5V_VCXO
C3101
X3102
0.1uF
16V
74.2125MHZ
VIN
VDD
1
4
GND
CLK
2
3
VCXO1_CLK_Y
FS_50ppm
X3102-*1
74.2125MHZ
VIN
VDD
1
4
GND
CLK
2
3
FS_10ppm
+2.5V_FPGA
+3.3V_FPGA
IC3101
W25Q40CLSNIG
CS
VCC
1
8
FPGA_SPI_CZ
DO[IO1]
HOLD[IO3]
2
7
FPGA_SPI_DO
WP[IO2]
CLK
3
6
GND
DI[IO0]
4
5
R3114
22
X3003
27MHz
X-TAL_1
GND_2
1
4
GND_1
X-TAL_2
24pF
2
3
+1.8V_VCXO
50V
24pF
C3112
50V
C3113
+1.8V_VCXO
OPT
OPT
IC3003
CDCE925PWR-AB(12.288MHZ+/-650PPPM)
XIN/CLK
XOUT
1
16
S0
S1/SDA
0
2
15
VCXO2_S0
R3124
VDD
S2/SCL
3
14
R3125
VCTR
Y1
100K
4
13
VCXO2_CTRL
C3111
0.1uF
GND_1
GND_2
5
12
16V
+2.5V_VCXO
VDDOUT_1
Y2
6
11
Y4
Y3
7
10
C3119
C3118
Y5
VDDOUT_2
8
9
0.1uF
0.1uF
16V
16V
FPGA_SPI_CLK
FPGA_SPI_DI
OPT
P3102
PH254ST-1*3P1-GP
1
+2.5V_VCXO
2
3
22
R3130
VCXO2_S1/SDA
R3131
22
VCXO2_S2/SCL
R3134
22
VCXO2_CLK_Y
LGE Internal Use Only
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