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TXBCLKP
TXBCLKN
TXB4P
TXB4N
TXB3P
TXB3N
TXB2P
TXB2N
TXB1P
TXB1N
TXB0N
TXB0P
TXACLKN
TXACLKP
TXA4P
TXA4N
TXA3P
TXA3N
TXA2N
TXA2P
TXA1P
TXA1N
TXA0P
TXA0N
LVDS Signals from 3D Depth IC to FPGA
FPGA_DEBUG_0
FPGA_DEBUG_1
FPGA_DEBUG_2
FPGA_DEBUG_3
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
IC10101
+2.5V_FPGA
XC6SLX16-3CSG324I
D3
E2
IO_L54N_M3A11_3
VCCO_3_1
E4
G4
IO_L54P_M3RESET_3
VCCO_3_2
E3
J2
IO_L50P_M3WE_3
VCCO_3_3
F6
J5
IO_L55P_M3A13_3
VCCO_3_4
F5
M4
IO_L55N_M3A14_3
VCCO_3_5
F4
R2
IO_L51P_M3A10_3
VCCO_3_6
F3
IO_L51N_M3A4_3
G6
IO_L53N_M3A12_3
FPGA Bank_3 :
H7
IO_L53P_M3CKE_3
2.5V Power Rail should be applied.
H6
IO_L49P_M3A7_3
H5
IO_L49N_M3A2_3
H4
IO_L44P_GCLK21_M3A5_3
H3
IO_L44N_GCLK20_M3A6_3
J7
IO_L47P_M3A0_3
J6
IO_L47N_M3A1_3
K6
IO_L45N_M3ODT_3
J3
IO_L40P_M3DQ6_3
K3
IO_L42N_GCLK24_M3LDM_3
K4
IO_L42P_GCLK25_TRDY2_M3UDM_3
K5
IO_L43N_GCLK22_IRDY2_M3CASN_3
L5
IO_L43P_GCLK23_M3RASN_3
L7
IO_L45P_M3A3_3
L6
IO_L31P_3
L4
IO_L39P_M3LDQS_3
+2.5V_FPGA
C2
IO_L83P_3
C1
IO_L83N_VREF_3
D2
OPT
IO_L52P_M3A8_3
10uF
4.7uF
2.2uF
D1
10uF
C10104
IO_L52N_M3A9_3
2.2uF
E1
16V
10V
10V
10V
IO_L50N_M3BA2_3
16V
F2
IO_L48P_M3BA0_3
F1
C10101
C10102
C10103
IO_L48N_M3BA1_3
C10115
G1
IO_L46N_M3CLKN_3
G3
Decouplingcapacitors forVCCO Bank3
IO_L46P_M3CLK_3
H1
IO_L41N_GCLK26_M3DQ5_3
H2
IO_L41P_GCLK27_M3DQ4_3
J1
IO_L40N_M3DQ7_3
K2
IO_L38P_M3DQ2_3
K1
IO_L38N_M3DQ3_3
L1
IO_L37N_M3DQ1_3
L2
IO_L37P_M3DQ0_3
M1
IO_L36N_M3DQ9_3
N2
IO_L35P_M3DQ10_3
N1
IO_L35N_M3DQ11_3
N3
IO_L1N_VREF_3
P1
IO_L34N_M3UDQSN_3
P2
IO_L34P_M3UDQS_3
P3
IO_L2N_3
T1
IO_L33N_M3DQ13_3
T2
IO_L33P_M3DQ12_3
U1
IO_L32N_M3DQ15_3
U2
IO_L32P_M3DQ14_3
M3
IO_L36P_M3DQ8_3
P4
IO_L2P_3
N4
IO_L1P_3
M5
IO_L31N_VREF_3
L3
IO_L39N_M3LDQSN_3
FPGA_LINK4A_TXCLKIN_P
FPGA_LINK4A_TXCLKIN_N
FPGA_LINK4A_TXIN2_P
FPGA_LINK4A_TXIN2_N
FPGA_LINK5A_TXCLKIN_P
FPGA_LINK5A_TXCLKIN_N
XILINX JTAG HDR FOR CONFIG OR CHIPSCOPE
P10104
12507WS-08L
+2.5V_FPGA
1
2
3
4
5
6
7
8
+2.5V_FPGA
9
R10101
R10102
4.7K
10K
/RESET2V5
IC10101
XC6SLX16-3CSG324I
F12
E7
IO_L51P_0
IO_L9P_0
E12
E8
LINK4A_LOCK_N
IO_L51N_0
IO_L9N_0
U15
F7
IO_L5P_2
IO_L7P_0
V15
E6
IO_L5N_2
IO_L7N_0
LINK3A_LOCK_N
T12
G8
IO_L19P_2
IO_L32P_0
F8
V12
IO_L19N_2
IO_L32N_0
N10
G11
IO_L20P_2
IO_L40P_0
P11
F10
FPGA_DEBUG_3
IO_L20N_2
IO_L40N_0
M10
F11
IO_L22P_2
IO_L42P_0
N9
E11
IO_L22N_2
IO_L42N_0
M11
D12
IO_L15P_2
IO_L47P_0
N11
C12
IO_L15N_2
IO_L47N_0
N7
C13
IO_L44P_2
IO_L50P_0
P8
A13
IO_L44N_2
IO_L50N_0
FPGA_DEBUG_0
M8
IO_L40P_2
N8
IO_L40N_2
N6
IO_L47P_2
P7
IO_L47N_2
IC10101
XC6SLX16-3CSG324I
+2.5V_FPGA
A17
B1
TCK
VCCAUX_1
D15
B17
TDI
VCCAUX_2
B18
E14
TMS
VCCAUX_5
D16
E5
TDO
VCCAUX_3
R16
E9
SUSPEND
VCCAUX_4
P13
G10
CMPCS_B_2
VCCAUX_6
V17
J12
DONE_2
VCCAUX_7
V2
K7
PROGRAM_B_2
VCCAUX_8
A1
M9
GND_1
VCCAUX_9
A18
P10
GND_2
VCCAUX_11
B13
P14
+1.2V_FPGA
GND_4
VCCAUX_12
B7
P5
GND_3
VCCAUX_10
C16
G7
GND_6
VCCINT_1
C3
H11
GND_5
VCCINT_3
D10
H9
GND_8
VCCINT_2
D5
J10
GND_7
VCCINT_5
E15
J8
GND_9
VCCINT_4
G12
K11
GND_12
VCCINT_7
G17
K9
GND_13
VCCINT_6
G2
L10
GND_10
VCCINT_9
G5
L8
+2.5V_FPGA
GND_11
VCCINT_8
H10
M12
GND_15
VCCINT_11
H8
M7
OPT
GND_14
VCCINT_10
J11
M17
10uF
GND_18
GND_26
10uF
4.7uF
0.47uF
0.47uF
C10113
J15
M2
0.47uF
GND_19
GND_24
J4
M6
16V
10V
25V
25V
25V
GND_16
GND_25
16V
J9
N13
GND_17
GND_27
C10116
K10
R1
C10105
C10107
C10109
C10111
GND_21
GND_28
K8
R14
GND_20
GND_31
Decouplingcapacitors forVCCAUX
L11
R18
GND_23
GND_32
L9
R4
GND_22
GND_29
R9
GND_30
T16
GND_33
U12
+1.2V_FPGA
GND_35
U6
GND_34
V1
GND_36
V18
OPT
GND_37
4.7uF
4.7uF
4.7uF
C10114
10uF
10uF
0.47uF
10V
10V
10V
25V
16V
16V
C10106
C10108
C10110
C10112
C10117
Decouplingcapacitors forVCCINT
FPGA Reset Level Shifter (3.3V to 2.5V)
+3.3V_NORMAL
+2.5V_FPGA
R10111
R10108
10K
4.7K
R10109
33
C
R10112
B
Q10102
2SC3052
10K
E
C
R10105
B
Q10101
/FPGA_RESET
2SC3052
10K
E
+3.3V_NORMAL
IC10102
KIA7029AF
SW10101
JTP-1127WEM
R10103
R10107
1
2
330
I
O
0
1
3
2
3
4
C10118
G
C10119
0.1uF
0.1uF
16V
16V
OPTIC_FPGA_RESET
R10110 0
/RESET2V5
/FPGA_RESET
OPT
LGE Internal Use Only
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