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+2.5V_FPGA
+12V
L10207
CIC21J501NE
+3.3V_NORMAL
IC10202
AOZ1072AI-3
L10209
3.6uH
NR8040T3R6N
PGND
LX_2
1
8
VIN
LX_1
2
7
C10213
0.1uF
R10226
2A
AGND
EN
10K
3
6
C10209
C10210
POWER_ON/OFF2_2
10uF
10uF
FB
COMP
4
5
25V
25V
R10222
C10214
20K
2200pF
EAN60922902
Vout=0.8*(1+R1/R2)
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
TYPICAL ?
mA
+2.5V_FPGA
+2.5V_FPGA
L10208
OPT
CIC21J501NE
4.7uF
0.47uF
0.47uF
10uF
10uF
OPT
10V
25V
25V
16V
16V
C10203
C10204
C10205
C10206
C10208
R10223
Decouplingcapacitors forVCCO Bank2
27K
1%
C10211
C10212
R1
22uF
22uF
R10224
10V
10V
4.3K
1%
C10215
100pF
50V
OPT
R10225
14K
R2
1%
+2.5V_FPGA
+2.5V_NORMAL
+3.3V_NORMAL
C10207
0.47uF
25V
L10203
BLM18PG121SN1D
FPGA_LINK3A_TXCLKIN_P
FPGA_LINK3A_TXCLKIN_N
FPGA_LINK3A_TXIN4_P
FPGA_LINK3A_TXIN4_N
FPGA_LINK3A_TXIN3_N
FPGA_LINK3A_TXIN3_P
FPGA_LINK3A_TXIN2_N
FPGA_LINK3A_TXIN2_P
FPGA_LINK3A_TXIN1_N
FPGA_LINK3A_TXIN1_P
FPGA_LINK3A_TXIN0_N
FPGA_LINK3A_TXIN0_P
FPGA_LINK4A_TXIN4_N
FPGA_LINK4A_TXIN4_P
FPGA_LINK4A_TXIN3_P
FPGA_LINK4A_TXIN1_N
FPGA_LINK4A_TXIN1_P
FPGA_LINK4A_TXIN0_N
FPGA_LINK4A_TXIN0_P
FPGA_LINK4A_TXIN3_N
R10220
FPGA_SPI_CZ
22
FPGA_SPI_DI
R10217 22
FPGA_SPI_CLK
FPGA_SPI_DO
22
R10209
FPGA_LINK5A_TXIN0_P
FPGA_LINK5A_TXIN1_P
FPGA_LINK5A_TXIN2_P
FPGA_LINK5A_TXIN3_P
FPGA_LINK5A_TXIN4_P
FPGA_LINK5A_TXIN0_N
FPGA_LINK5A_TXIN1_N
FPGA_LINK5A_TXIN2_N
FPGA_LINK5A_TXIN3_N
FPGA_LINK5A_TXIN4_N
+3.3V_FPGA
+3.3V_FPGA
W25Q40CLSNIG
L10204
BLM18PG121SN1D
CS
1
FPGA_SPI_CZ
DO[IO1]
2
FPGA_SPI_DO
WP[IO2]
3
GND
4
+2.5V_FPGA
R10204
4.7K
OPT
R10216
0
+3.3V_FPGA
+2.5V_FPGA
/RESET2V5
IC10101
XC6SLX16-3CSG324I
R3
P9
IO_L62P_D5_2
VCCO_2_1
U3
R12
IO_L65P_INIT_B_2
VCCO_2_3
T4
R6
IO_L63P_2
VCCO_2_2
U5
U14
IO_L49P_D3_2
VCCO_2_6
T5
U4
IO_L48N_RDWR_B_VREF_2
VCCO_2_4
V7
U9
IO_L43N_2
VCCO_2_5
U7
IO_L43P_2
T7
IO_L46N_2
V8
IO_L41N_VREF_2
U8
IO_L41P_2
T8
IO_L31N_GCLK30_D15_2
V10
IO_L30N_GCLK0_USERCCLK_2
U10
IO_L30P_GCLK1_D13_2
T10
IO_L29N_GCLK2_2
U11
IO_L23P_2
T11
IO_L16N_VREF_2
V13
IO_L14N_D12_2
U13
IO_L14P_D11_2
T13
IO_L3N_MOSI_CSI_B_MISO0_2
V14
IO_L12N_D2_MISO3_2
T14
IO_L12P_D1_MISO2_2
T15
IO_L1N_M0_CMPMISO_2
V16
IO_L2N_CMPMOSI_2
U16
IO_L2P_CMPCLK_2
V6
IO_L45N_2
V3
IO_L65N_CSO_B_2
V4
IO_L63N_2
V5
IO_L49N_D4_2
V9
IO_L32N_GCLK28_2
T6
IO_L45P_2
V11
IO_L23N_2
T3
IO_L62N_D6_2
R15
IO_L1P_CCLK_2
R13
IO_L3P_D0_DIN_MISO_MISO1_2
N12
IO_L13P_M1_2
P12
IO_L13N_D10_2
R11
IO_L16P_2
R10
IO_L29P_GCLK3_2
R8
IO_L31P_GCLK31_D14_2
T9
IO_L32P_GCLK29_2
R7
IO_L46P_2
R5
IO_L48P_D7_2
N5
IO_L64P_D8_2
P6
IO_L64N_D9_2
+2.5V_FPGA
+2.5V_FPGA
Mode Pins --> determine configuration mode
Parallel configuration mode bus is auto-detected by the configuration logic.
M[1:0] = 10
CCLK Direction : Input
Bus Width : 8, 16
+2.5V_FPGA
IC3101
VCC
8
HOLD[IO3]
7
CLK
6
FPGA_SPI_CLK
DI[IO0]
5
R3114
FPGA_SPI_DI
22
FPGA Bank_2 :
2.5V Power Rail should be applied.
LGE Internal Use Only
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