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+3.3V_SERDES
+3.3V_SERDES
+3.3V_SERDES
+3.3V_SERDES
VDD33_1
1
NC_1
2
THERMAL
GPIO0
3
49
GPIO1
2.2K
4
IC10501
R10512
DC_B
5
+2.5V_SERDES
RS
DS32EL0421
6
VDD25_1
7
NC_2
8
DE_EMPH0
9
DE_EMPH1
10
GPIO2
11
NC_3
12
22K
+2.5V_SERDES
R10502
PWM_DIM
PWM_DIM2
ERROR_OUT
LOCAL_DIM_EN
BPL_IN
A_DIM
+3.3V_SERDES
+3.3V_SERDES
+3.3V_SERDES
+3.3V_SERDES
VDD33_1
1
NC_1
2
THERMAL
GPIO0
3
49
GPIO1
2.2K
4
IC10503
R10557
DC_B
5
+2.5V_SERDES
RS
DS32EL0421
6
VDD25_1
7
NC_2
8
DE_EMPH0
9
DE_EMPH1
10
GPIO2
11
NC_3
12
22K
+2.5V_SERDES
R10517
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3V_SERDES
+3.3V_SERDES
C10510
+2.5V_SERDES
VDD33_2
5pF
36
50V
VDD25_5
35
SMB_CS
34
FPGA_LINK1A_SMB_CS
SCK
R10537 0
33
FPGA_A_SCK
SDA
32
FPGA_A_SDA
LOCK
31
LINK1A_LOCK_N
RESET
R10533 0
30
SERDES_RESET
RSVD
29
+3.3V_SERDES
R10559 0
VDDPLL
28
LF_CP
2.7K
27
Place Close TO IC10501
0.1uF
R10501
LF_REF
26
C10543
+2.5V_SERDES
VDD25_4
C10503
25
22uF
10V
C10543,R10501 CLOSER TO IC10501
LINK1A_DOUT_N
LINK1A_DOUT_P
+3.3V_SERDES
+3.3V_SERDES
+3.3V_SERDES
+3.3V_SERDES
VDD33_1
1
NC_1
2
THERMAL
GPIO0
3
2.2K
GPIO1
4
R10587
DC_B
5
+2.5V_SERDES
RS
6
VDD25_1
7
NC_2
8
DE_EMPH0
9
DE_EMPH1
10
GPIO2
11
NC_3
12
22K
+2.5V_SERDES
R10578
+3.3V_SERDES
+2.5V_SERDES
VDD33_2
36
VDD25_5
35
SMB_CS
34
FPGA_LINK3A_SMB_CS
SCK
R10538 0
33
FPGA_A_SCK
SDA
32
FPGA_A_SDA
LOCK
31
LINK3A_LOCK_N
RESET
R10519 0
30
SERDES_RESET
RSVD
29
+3.3V_SERDES
R10520 0
VDDPLL
28
LF_CP
2.7K
Place Close TO IC10503
27
0.1uF
LF_REF
R10549
26
C10516
+2.5V_SERDES
VDD25_4
C10562
25
22uF
10V
R10549,C10516 CLOSER TO IC10503
LINK3A_DOUT_N
LINK3A_DOUT_P
FPGA_A_SCK
+3.3V_SERDES
+3.3V_SERDES
+3.3V_SERDES
FPGA_A_SDA
+3.3V_SERDES
C10511
5pF
50V
2.2K
R10553
+2.5V_SERDES
+3.3V_SERDES
+2.5V_SERDES
VDD33_2
36
VDD25_5
35
SMB_CS
49
34
FPGA_LINK5A_SMB_CS
R10582 0
SCK
33
IC10504
FPGA_A_SCK
SDA
32
FPGA_A_SDA
DS32EL0421
LOCK
31
LINK5A_LOCK_N
RESET
R10581 0
30
SERDES_RESET
RSVD
29
+3.3V_SERDES
VDDPLL
R10583 0
28
LF_CP
2.7K
Place Close TO IC10503
27
0.1uF
LF_REF
R10586
26
C10526
+2.5V_SERDES
VDD25_4
25
C10549,R10516 CLOSER TO IC10503
LINK5A_DOUT_N
LINK5A_DOUT_P
+3.3V_SERDES
+3.3V_SERDES
+3.3V_SERDES
+3.3V_SERDES
2.2K
R10552
+2.5V_SERDES
VDD33_1
VDD33_2
1
36
NC_1
VDD25_5
2
35
THERMAL
GPIO0
SMB_CS
3
34
49
GPIO1
SCK
R10523 0
4
33
IC10502
FPGA_A_SCK
DC_B
SDA
5
32
FPGA_A_SDA
RS
DS32EL0421
LOCK
6
31
VDD25_1
RESET
7
30
NC_2
RSVD
8
29
DE_EMPH0
VDDPLL
R10541 0
9
28
DE_EMPH1
LF_CP
2.7K
10
27
GPIO2
LF_REF
R10550
11
26
NC_3
VDD25_4
12
25
C10513,R10550 CLOSER TO IC10502
LINK2A_DOUT_N
22K
+2.5V_SERDES
LINK2A_DOUT_P
R10515
+3.3V_SERDES
+3.3V_NORMAL
L10506
BLM18PG121SN1D
C10537
C10538
C10534
10uF
0.1uF
22uF
16V
16V
10V
SERDES_RESET
VDD33_1
VDD33_2
1
36
NC_1
VDD25_5
2
35
THERMAL
GPIO0
SMB_CS
3
49
34
GPIO1
SCK
R10524 0
4
33
IC10500
FPGA_A_SCK
DC_B
SDA
5
32
FPGA_A_SDA
RS
DS32EL0421
LOCK
6
31
VDD25_1
RESET
7
30
NC_2
RSVD
8
29
DE_EMPH0
VDDPLL
R10540 0
9
28
DE_EMPH1
LF_CP
10
27
2.7K
GPIO2
LF_REF
R10551
11
26
NC_3
VDD25_4
12
25
C10517,R10551 CLOSER TO IC10500
LINK4A_DOUT_N
22K
+2.5V_SERDES
LINK4A_DOUT_P
R10516
LG1152 A0
Interface block
+3.3V_SERDES
+2.5V_SERDES
FPGA_LINK2A_SMB_CS
LINK2A_LOCK_N
R10542 0
SERDES_RESET
+3.3V_SERDES
Place Close TO IC10502
0.1uF
C10513
+2.5V_SERDES
C10561
22uF
10V
+2.5V_SERDES
+2.5V_FPGA
L10507
BLM18PG121SN1D
C10535
C10536
10uF
0.1uF
16V
16V
+3.3V_SERDES
OPT
0
OPTIC_SERDES_RESET
R10534
+3.3V_SERDES
+2.5V_SERDES
FPGA_LINK4A_SMB_CS
LINK4A_LOCK_N
R10522 0
SERDES_RESET
+3.3V_SERDES
Place Close TO IC10500
0.1uF
C10517
+2.5V_SERDES
C10560
22uF
10V
72
100
LGE Internal Use Only
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