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Status Register
b+00
15
14
13
h
Write
Read
Control Register
b+02
15
14
13
h
Write
Read
The Status Register is a read only register at address 00
(LSB) in A24 memory. The default value of this register 01
12
11
10
9
8
Not used
•
CPRDY: Command/Parameter Ready. A "1" in this bit indicates that
the Command and Parameter registers are empty and available for the
next command from the host controller. A "0" indicates that the
DONE bit in the Command Status Register (address 26
valid.
•
IREQn: Interrupt Request Status Bit. A "1' indicates the respective
port (1 through 4) has an interrupt request. There are seven interrupt
sources for each port: FIFO decreased below half full, one pre-defined
BLOCK received, Receiver time-out, Transmit FIFO became empty,
an error occurred, the termination character is received, or a
self-generated interrupt occurs. For detailed information, refer to the
Port Interrupt Status/Control Register. Any interrupt source sets
IREQn if that source is enabled. If Portn and the global system
interrupt is enabled, a "1" in an any of these bits will generate an
interrupt to the host controller.
•
At power-on or reset, all bits are "0" except CPRDY which has a value
of "1".
The Control Register is a read/write register at address 002
The default value of this register is 00
12
11
10
9
8
Not used
•
IENn: Enable Interrupt of Port n. The bit must be set to a "1" for that
port to generate an interrupt to the host controller.
•
IENABLE: Global Interrupt Request Enable. Bit must be set to a "1"
for interrupts to occur.
•
SRESET: Soft Reset. Writing a "1" to this bit followed by writing a
"0" causes the module to its soft reset state.
•
At power-on or reset, all bits are "0".
7
6
5
4
Undefined
IREQ3
h
7
6
5
4
Undefined
IEN3
IEN2
Register Programming Information
(MSB) and 01
h
.
h
3
2
1
IREQ2
IREQ1
IREQ0
) may not be
h
in A24 memory.
h
.
3
2
1
IEN1
IEN0
IENABLE
h
0
CPRDY
0
SRESET
65
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