Motorola M68EM05C0 User Manual page 13

M68EM05C0UM/D
MOTOROLA
Freescale Semiconductor, Inc.
Table 1. Connector J2 Signal Descriptions
Pin Mnemonic
1, 4, 19, 24,
GND
38, 40
2 EMV
CC
3, 6, 8, 10, 12,
NC
14, 16, 18, 23
5, 7, 9, 11, 13, A15,
15, 17, 21 A14–A8
20, 22, 26, 28, A/PD7–
30, 32, 34, 36 A/PD0
25, 27, 29, 31,
AD7–AD0
33, 35, 37, 39
Table 2. Connector J3 Signal Descriptions
Pin Mnemonic
1 T-IRQ
2 RESET
3, 5, 7, 11, 12,
13, 15, 17,19,
NC
21, 23, 25,
29, 30, 34
PC3–
4, 6, 8, 10
PC0
9,14, 27, 32,
GND
38, 40
16 PB0
General Description
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Signal
GROUND
+5 Vdc POWER — Connection to the system
voltage V
CC
No connection
Upper address lines — These upper address lines
constitute the upper address byte. A15 is active
low (inverted). A14-A8 are active high.
In muxed mode, these lines are port D (bits 7–0) —
general-purpose I/O lines controlled by software
via data direction and data registers.
In non-muxed mode, these lines are the dedicated
lower address byte A7–A0.
In muxed mode, these lines are the multiplexed
lower address byte and the data byte.
In non-muxed mode, these lines are the data byte.
Signal
TARGET INTERRUPT REQUEST — Active-low
input signal from the target that asynchronously
applies an MCU interrupt
Active-low bidirectional signal to/from the target
system driven low to pull the MCU into reset
No connection
PORT C (bits 3–0) — General-purpose I/O lines
controlled by software via data direction and data
registers
GROUND
PORT B bit 0 — General-purpose I/O lines
controlled by software via data direction and data
registers
Becomes the timer compare (TCMP) output pin
when the output compare mode feature of the
16-bit timer subsystem is enabled
General Description
Connector Information
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