Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Technology Corp.
Page 2 Renesas Electronics product depends on the product’s quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as “Specific”...
Page 3 Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 4 General Precautions in the Handling of ASSP Products The following usage notes are applicable to all ASSP products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of ASSP Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 5 Refer to the text of the manual for details. The following documents apply to the Ethernet PHY products . Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Electronics Web site. Document Description Document Title Document No.
Page 6 Notation of Numbers and Symbols Abbreviation Full Form Register p.n Register n at PHY address p Register p.n.b Bit ‘b’ in register address n at PHY address p PHY stands for PHY address “0” or “1” so this would mean Register PHY.n register n in any of the two PHYs, can by PHY address 0 or PHY address 1.
Page 7 List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus Input/Output IrDA Infrared Data Association Least Significant Bit...
Page 8: Table Of Contents
Table of Contents General Description ............12 Overview of product features ............... 12 Special product features ................13 Applications ....................13 Pin Functions ..............14 Pin-out Information ..................14 2.1.1 Pin Layout ........................14 2.1.2 Port Pins ........................... 15 System Diagram ..............17 Device block diagram ..................
Page 9 5.4.4 Scrambler / Descrambler ....................34 5.4.5 5B/4B Encoding / Decoding .................... 34 Functional Description .................. 36 5.5.1 Collision detection ......................36 5.5.2 Carrier Sense detection ....................36 5.5.3 Auto Crossover (MDI/MDI-X) ..................36 5.5.4 Auto-Polarity ........................37 5.5.5 Auto-Negotiation......................37 5.5.6 Bad Line recognition .......................
Page 10 1588 Clock Control ..................65 7.3.1 CLOCK_STATUS Register 6.0 ..................66 7.3.2 CLOCK_READ Register 6.1 ................... 66 7.3.3 CLOCK_WRITE Register 6.2 ................... 66 7.3.4 CLOCK_OFFSET Register 6.3 ..................67 7.3.5 CLOCK_DRIFT Register 6.4 .................... 68 Frame Handling Unit ..................68 7.4.1 One step mode .........................
Page 11 Physical dimensions ............103 Revision history .............. 104 R19UH0083ED0100 User Manual...
Page 12: General Description
General Description The extended dual-channel 10/100 Ethernet PHYs uPD60620 uPD60620A and uPD60621A are fully integrated Physical layer devices to connect to standard IEEE802.3 Ethernet networks. Today’s industrial networking standards often implement daisy-chain or ring structures, in which a dual-channel PHY configuration makes a perfect fit.
Page 13: Special Product Features
 Enables software power-up/down and automatic power up/down by energy detection  Single 3.3 V power supply with optional separated 1.5V  Operating temperature: T = -40 to +85°C (T from -40 to +125°C) ambient junction  LQFP80 package (7 mm x 7 mm) 1.2 Special product features ...
Page 14: Pin Functions
Pin Functions 2.1 Pin-out Information 2.1.1 Pin Layout R19UH0083ED0100 User Manual...
Page 15: Port Pins
2.1.2 Port Pins Power Supply Pins Comment REGBVDD 70, 71 3.3V voltage regulator input REGBGND 74, 75 GND for voltage regulator VDDIO 32, 50, 66 3.3V/2.5V IO power supply VDD33ESD 3,3V input P1AGND, P0AGND 8, 14 Analog GND for PHY REGAGND Analog GND for regulator REGAVDD...
Page 16 P1TXD0 P1TXD1 P1TXD2 GPIO17 P1TXD3 PHY1MII GPIO16 P1TXERR GPIO15 P1TXEN P1TXCLK Clock input in XCLK0 I XCLK0 50MHz (RMII) 33 external clock mode Open in external XCLK1 O XCLK1 clock mode P1RXD0 P1RXD1 P1RXD2 GPIO14 P1RXD3 GPIO13 PHY1MII P1RXDV P1CRS_DV P1RXERR P1RXCLK P1CRS...
Page 17: System Diagram
The picture below shows the system diagram. The PHY is connected to the MAC through a MII or RMII interface. On the other side it is connected either to a CAT5 cable through magnetics or to a fibre cable. Renesas Renesas R19UH0083ED0100...
Page 18: Device Block Diagram
3.1 Device block diagram The device consists of two PHY’s each connected to a PTP Framer block used to de-/encode the PTP frames and timestamp them, a PTP timer block containing the PTP clock, and an I/O block for general configuration and I/O handling. The PTP support is only available on the uPD60621A.
Page 19: Global Hardware Description
Global Hardware Description The device consists of two Ethernet PHYs combined in a single package. In addition it includes a control block which is used to control shared resources such as LED outputs, interrupts, and low-power modes. All are accessible through a two wire bidirectional Serial Management Interface.
Page 20: General Smi Control Register 7.31
4.2 General SMI Control Register 7.31 The following register is used for configuration of the SMI: Name Description Mode Reset 1: Initiates a hardware reset of the complete device (stays active until RESET cleared by software) 0: Release Reset SMI_SHORT 1: Enable short preamble support.
Page 21: Power Control Register 7.30
4.3 Power Control Register 7.30 The following register is used for configuration of the power options: Name Description Mode Reset 15:13 POWER_ST 100: Device ready. ATUS Other than 100: Device not ready Reserved STOP 1: Device is disabled; only access to registers 7.25-7.31 in the GLOBAL_CONFIG area is possible.
Page 22: Phy Status Register 7.28
4.4 PHY Status Register 7.28 The following register shows the status of the PHYs. Name Description Mode Reset 15:10 Reserved Write as 0 PHY1_LINK 0: PHY 1 has no link 1: PHY 1 has link PHY0_LINK 0: PHY 0 has no link 1: PHY 0 has link Reserved Write as 0...
Page 23: Phy Led Status Register 7.24
4.6 PHY LED Status Register 7.24 The following register shows the status of the PHYs after power up. To read the LED status for the PHYs first PHY_SELECT must be written with the number of the required PHY and then the data for this PHY can be read from the register. The ACTIVE_LED_BLINK bit can be used to control the LED outputs of the device.
Page 24: Interrupt Status Register 7.20
4.7 Interrupt Status register 7.20 To have a centralized register to get a summary of all possible interrupt sources an interrupt status register is placed at the top level in addition to the specific interrupt registers. The bits in this register are only set if the corresponding interrupt is enabled in the interrupt source modules.
Page 25: Interrupt Mask Register 7.21
4.8 Interrupt Mask register 7.21 To provide a summary of all possible interrupt sources an interrupt mask register is placed at the top level in addition to the specific interrupt registers. Note that this is just an additional option to mask all interrupts at a central register; all Interrupts need to be enabled at their respective location within the PHY or PTP register set.
Page 26: Gpio
4.9 GPIO The GPIO pins can be configured depending on the application. Thus it is possible to repurpose unused pins for additional LEDs or PTP I/O. It is also possible to use the LED pins for PTP debug signals. The GPIO registers are located in the GLOBAL_CONFIG address range.
Page 27: Gpio_Config_1 Register 7.1
(uPD60621A only) 0111: GPIO is Output for P0LINKLED 1000: GPIO is Output for P1LINKLED 1001: GPIO is Output for P0_100BT- 1010: GPIO is Output for P1_100BT- 1011: GPIO is Output for P0ACTIVELED 1100: GPIO is Output for P1ACTIVELED 1101: GPIO is Output for INT 1110: GPIO is Output for CHIP_SYNC (uPD60621A only) 1111: GPIO is Input...
Page 28: Gpio_Config_2 Register 7.2
4.9.3 GPIO_CONFIG_2 Register 7.2 Name Description Mode Reset 15:12 GPIO11 MII mode: always P0TXD2, 1111 in RMII regardless of setting. RMII mode: coding is same as GPIO0 1110: SOF_TX0 Start of frame PHY0 TX path (uPD60621A only) 11:8 GPIO10 MII mode: always P0TXD3, 1111 in RMII regardless of setting.
Page 29: Gpio_Config_4 Register 7.4
4.9.5 GPIO_CONFIG_4 Register 7.4 Name Description Mode Reset 15:12 GPIO19 PHY 0 in FX mode: always P0SD 1110 P0COL PHY 0 in TX mode: coding is same as GPIO0 except 1110: P0COL 11:8 GPIO18 PHY 1 in FX Mode: always P1SD 1110 P1COL PHY 1 in TX mode: coding is same as GPIO0 except...
Page 30: Strap Options
4.10 Strap Options The device offers several configurations which can be selected as strap options. The related I/Os have integrated 40 kΩ pull-up or pull-down resistors which configure the device as described below. To change this configuration an external resistor of maximum 5 kΩ must be connected to the pin. An external resistor supporting the internal resistor is also advisable in case the device is used in a very noisy environment.
Page 31 0: Synchronous mode for TXCLK. TXCLK is synchronous to XCLK0. This must be used for MACs that supply the MII TX data synchronously to the XCLK0 signal. P1TXCLK 1, PU 1: Asynchronous mode for TXCLK. This mode reduces the TX Latency, but requires a MAC that handles the TXCLK signal to supply the MII TX data.
Page 32: Phy
5.1 General Description The device contains two PHYs. The block diagram for each is shown below: R19UH0083ED0100 User Manual...
Page 33: Clock Generator Pll
5.2 Clock Generator PLL The PLL is a 125 MHz PLL which generates the clock for the 125 MHz part. It generates 32 output phases. The DSP selects which of these phases is used to sample the incoming signal. A single PLL is used for both PHYs. Therefore a Power Down of a PHY will only power down the PLL if both PHYs are powered down.
Page 34: Nrzi/Mlt-3 Encoding / Decoding
5.4.3 NRZI/MLT-3 Encoding / Decoding MLT3 is a specific version of a NRZI coding using a tri-level code where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. Basically it uses the NRZI coding as input but the ‘1’...
Page 35 PCS code- MII (TXD/RXD) Name Interpretation group [4:0] [3:0] 1 1 1 1 0 0 0 0 0 Data 0 0 1 0 0 1 0 0 0 1 Data 1 1 0 1 0 0 0 0 1 0 Data 2 1 0 1 0 1 0 0 1 1...
Page 36: Functional Description
5.5 Functional Description 5.5.1 Collision detection When transmissions from two stations overlap, the resulting contention is called a collision. Collisions occur only in half duplex mode, where a collision indicates that there is more than one station attempting to use the shared Physical medium. 5.5.2 Carrier Sense detection Carrier Sense (CRS) is asserted by the PHY when either transmit or receive medium is non-idle.
Page 37: Auto-Polarity
5.5.3.2 Auto-Crossover when using Autonegotiation or 10BT Mode Since the auto-negotiation’s method of communication builds upon the link pulse mechanism employed by 10BASE-T MAUs to detect the status of the link, the energy detection upon FLPs bursts is the same as the NLPs. The NLP is a pulse transmitted every 16±8 ms.
Page 38 In case a pulse is distorted the process will start over again. To improve the linkup time for two Renesas PHYs the nominal 16ms frame rate is reduced to allowed 8 ms and shortening the frame transmission time. In this case two Renesas PHYs are able to negotiate within 72 ms without hurting the IEEE spec.
Page 39 5.5.5.2 Disabling Auto-Negotiation Auto-negotiation can be disabled by register setting or by setting the appropriate strap pins. When auto-negotiation is disabled, the speed and duplex modes are decided by setting management interface registers or Parallel Detection. 5.5.5.3 Priority Resolution There are four possible operating modes. In the order of priority these are: 100M full duplex (highest priority) 100M half duplex 10M full duplex...
Page 40: Bad Line Recognition
5.5.5.5 Re-negotiation When auto-negotiation is enabled, it may be re-started by one of the following events: 1. Link status is down. 2. Setting Auto-Negotiation Restart bit to high. Auto-negotiation is started (not re-started) when 1) Hardware reset, 2) Software reset or 3) setting Auto-Negotiation Enable from low to high. 5.5.5.6 Parallel Detection The parallel detection function allows detection of link partners that support 100BASE-TX and/or 10BASE-T, but do not support auto-negotiation or are set to...
Page 41 5.5.6.1 BER-Monitor The PHY can continuously measure the bit error rate (BER) on the line and trigger an interrupt or put the link down if a configurable threshold is reached. Bit errors are detected by checking the received symbols against the list of allowed symbols.
Page 42 23.10:7 BER_WINDOW Length of time for BER counter in 1 (0.01 0.005 * 2^n ms 0: BER counter functions disabled 1: 0.01 ms 2: 0.02 ms 3: 0.04 ms … 14: 81.92 ms 15: unlimited run window. Writing a 0 resets the BER counter and restarts the time window.
Page 43 5.5.6.2 FEQ-Monitor In order to optimize the reception of the incoming data, the DSP continuously adapts its filters to the incoming signal. To be able to monitor the line quality, one of the DSP filter coefficients can be monitored and an interrupt or link down can be triggered if programmable limits are exceeded.
Page 44 The following picture gives an example of the value of the FEQ coefficient for several line lengths (in meters.) The following picture gives an example of the dependency of the FEQ coefficient on the resistance of the line. The 0 Ohm resistance is the value for a 1 meter line, for the other values a resistor has been added to the RX line.
Page 45: Latency
Both the latency itself and the variation in latency (jitter) should be as small as possible. Although the Renesas PHY has already a very short latency, the PHY has a special mode that will reduce the latency even further. This mode is called “J-only mode”...
Page 46: Repeater / Media Converter
5.5.9 Repeater / Media converter This PHY supports channel to channel loopback mode and can be used as physical repeater. In this mode, the received frame at each port is directly forwarded to the other port. Channel to channel loopback mode is configured by strap option or register setting.
Page 47: Phy Register List
5.6 PHY Register List The PHY registers can be accessed at PHY address 0 for PHY 0 or PHY address 1 for PHY 1. These registers control only the PHY they belong to. Some of these registers are duplicated on the PHY address 7 registers to ease software handling.
Page 48: Register Phy.1 - Basic Control
5.6.2 Register PHY.1 - Basic Control Name Description Mode Default 100BASE_T4 1 = 100BASE-T4 able 0 = no 100BASE-T4 ability 100BASE_TX_ 1 = 100BASE-TX ability with full FULL_DUPLEX duplex 0 = no 100BASE-TX full duplex ability 100BASE_TX_ 1 = 100BASE-TX ability with half HALF_DUPLEX duplex 0 = no 100BASE-TX half duplex...
Page 49: Register Phy.3 - Phy Identifier
5.6.4 Register PHY.3 - PHY Identifier Name Description Mode Default 15:10 PHY ID Assigned to the 19th through 0x0a NUMBER 24th bits of the OUI MODEL Manufacturer’s model number NUMBER REVISION Manufacturer’s revision number NUMBER 5.6.5 Register PHY.4 - Auto-Negotiation Advertisement Name Description Mode...
Page 50: Register Phy.5 - Auto-Negotiation Link Partner Ability (Base Page)
5.6.6 Register PHY.5 - Auto-Negotiation Link Partner Ability (Base Page) Name Description Mode Default NEXT PAGE 1 = additional next page will follow 0 = last page ACKNOWLEDGE 1 = successfully received link partner’s link code word 0 = not successfully received link partner’s link code word REMOTE FAULT 1 = remote fault condition 0 = no remote fault condition...
Page 51: Register Phy.5 - Auto-Negotiation Link Partner Ability (Next Page)
5.6.7 Register PHY.5 - Auto-Negotiation Link Partner Ability (Next Page) Name Description Mode Default NEXT PAGE 1 = additional next page will follow 0 = last page ACKNOWLEDGE 1 = successfully received link partner’s link code word 0 = not successfully received link partner’s link code word MESSAGE 0 = unformatted page...
Page 52: Register Phy.7 - Auto-Negotiation Next
5.6.9 Register PHY.7 - Auto-Negotiation Next Page Transmit Name Description Mode Default NEXT PAGE 1 = next page exists 0 = next page does not exist RESERVED Write as “0”, ignore on read MESSAGE PAGE 1 = message page 0 = unformatted page ACKNOWLEDGE2 0 = cannot comply with message 1 = will comply with message TOGGLE...
Page 53: Register Phy.17 - Mode Control/Status
5.6.11 Register PHY.17 - Mode Control/Status Name Description Mode Default RESERVED Write as 0; ignore on read. FASTRIP 10BASE-T fast mode: 0 = normal operation NASR 1 = activates PHYT_10 test mode Note: this bit can be used for simulation EDPWRDOWN Enable the energy detect power- down mode:...
Page 54 will not be written to RESERVED Write as 0, ignore on read DCD_PAT_GEN When in test mode, 1 = Enables DCD measuring pattern generation RESERVED Write as 0, ignore on read FORCE GOOD 1 = Force 100BASE-X link LINK active STATUS 0 = normal operation Note: this bit should be set only...
Page 55: Register Phy.18 - Special Modes
5.6.12 Register PHY.18 - Special Modes Name Description Mode Default 15:11 Reserved Write as 0, ignore on read NASR FX_MODE Enable 100BASE-FX mode Strap option 1 = FX mode enable NASR When PHYMODE should be set to “0011” or “0010” only. Reserved Write as “0”.
Page 56: Register Phy.20 - Reserved
T_EL_BUF_OVF Transmitter elastic overflow RO/LH T_EL_BUF_UDF Transmitter elastic underflow RO/LH R_EL_BUF_OVF Receiver elastic overflow RO/LH R_EL_BUF_UDF Receiver elastic underflow RO/LH reserved Ignore on read 5.6.14 Register PHY.20 – Reserved Name Description Mode Default 15:0 Reserved Ignore on read 5.6.15 Register PHY.21 – Reserved Name Description Mode...
Page 57: Register Phy.23 - Ber Counter
5.6.17 Register PHY.23 – BER Counter Name Description Mode Default BER_LNK_OK Link quality indication – indicates state of link monitor FSM. '0' – FSM is not in 'Good Link' state '1' – indicates FSM in 'Good Link' state Will go high as soon as the counter is below the trigger level after start up.
Page 58: Register Phy.24 - Feq Monitor Register
5.6.18 Register PHY.24 – FEQ monitor Register Default Name Description Mode 15:0 FEQ_DELTA Minimum change of value W 0xFFFF compared to the reference value latched when the monitor is enabled, which will trigger the FEQ interrupt and link down. If the FEQ value differs by more than that value, the link goes down, if the BER_CNT_LNK_EN is 1 and the BER Monitor is...
Page 59: Register Phy.25 - Diagnosis Control/Status Register
5.6.19 Register PHY.25 – Diagnosis Control/Status Register Name Description Mode Default Reserved Write with 0; ignore on read DIAG_INIT When set to '1' , create one (self cycle pulse - init TDR test cleared) 13:8 ADC_MAX_ Shows the signed VALUE maximum/minimum value of the reflected wave.
Page 60: Register Phy.26 - Diagnosis Counter Register
5.6.20 Register PHY.26 – Diagnosis Counter Register Name Description Mode Default Minimum time after which the counter stops. Used to filter out any pulses or reflections generated from the local 15:8 CNT_WINDOW connector or similar sources. One tick equals approximately 0.8m Indicates the location of the received signal which exceeded...
Page 61: Register Phy.28 - Reserved
5.6.22 Register PHY.28 - Reserved Do not write or read this register 5.6.23 Register PHY.29 - Interrupt Source Flags Name Description Mode Default 15:11 Reserved Ignore on Read INT10 BER counter trigger INT9 FEQ trigger Reserved Ignore on read INT7 1 = ENERGYON generated INT6 1 = auto-negotiation complete...
Page 62: Register Phy.31 - Phy Special Control/Status
5.6.25 Register PHY.31 - PHY Special Control/Status Name Description Mode Default 15:14 Reserved Write as 0. ignore on read. Reserved Write as 0. ignore on read. AUTODONE Auto-negotiation done indication 1 = auto-negotiation is done 0 = auto-negotiation is not done disabled (or not active) 11:7 Reserved...
Page 63: External Components
External Components 6.1 Clock The devices can be operated on an external 25 MHz clock in MII mode or an external 50 MHz clock in RMII mode. In addition for MII mode it contains an internal oscillator which may generate the required 25 MHz clock using an external 25 MHz crystal connected to the pins XCLK0 and XCLK1.
Page 64: Support Of Ieee1588 (Upd60621A Only)
Support of IEEE1588 (uPD60621A only) Renesas Electronics’ Ethernet PHY implements the precision time protocol (PTP) according to IEEE1588 to support the requirements of higher precision and faster production. The PHY supports IEEE1588 V1 and V2 including transparent clock mode and one-step or two-step mode.
Page 65: Register Access To Ptp
There are two ways in which timestamps can be transmitted between the nodes. One way is called “One Step”. In this mode the timestamps for transmit frames are directly embedded in the telegram itself.. This approach reduces the software overhead at the expense of increased latency. The other method is called a “Two Step”...
Page 66: Clock_Status Register 6.0
7.3.1 CLOCK_STATUS Register 6.0 Name Description Mode Default EN_OFFSET_ 1: Enable offset correction CORR 0: Disable offset correction Automatically cleared after the offset correction is finished. OFFSET_RUN 1: offset correction in process 0: offset correction done EN_DRIFT_C 1: enable drift correction 0: disable drift correction 11:9 CLOCK_READ...
Page 67: Clock_Offset Register 6.3
7.3.4 CLOCK_OFFSET Register 6.3 This register is used to adjust the clock to a new value. To avoid sudden jumps the offset is not added all at once; instead the “OFFSET” is added/subtracted to the clock value after “OFFSET_INTERVAL” for “OFFSET_COR_COUNT” times. Thus the clock is slowly adjusted to the new value value and jumps are avoided.
Page 68: Clock_Drift Register 6.4
7.3.5 CLOCK_DRIFT Register 6.4 This register contains a correction value, which can be used to continuously correct the clock value to compensate for oscillator drift. The value in the DELTA_VAL register is summed up every clock cycle (125MHz), as soon as the sum has exceeded 0x3fffffff a value of 1 an additional ns is depending on the DELTA_SIGN bit added/subtracted from the clock value.
Page 69: One Step Mode
7.4.1 One step mode For one-step PTP the timestamp is stored in the outgoing timestamp latch and is then integrated into the timestamp field of the frame before it is sent. The CRC is also corrected accordingly. Note that for one-step mode the latency through the PHY is increased as the insertion of the time stamp in the frame requires some processing of the frame.
Page 70 thus the complete line delay is known. Although this method is more complex than the End to end transparent clock it offers much faster reconfiguration in case of line breaks. R19UH0083ED0100 User Manual...
Page 71: Timestamp Status Register 6.6
7.4.4 Timestamp Status Register 6.6 The Timestamp Status register shows the status for each buffer: Name Description Mode Default 15:12 Reserved write as 0, ignore on read BUF_EMPTY_TX_PHY1 Buffer empty for TX bufferPHY1 BUF_EMPTY_RX_PHY1 Buffer empty for RX buffer PHY1 BUF_EMPTY_TX_PHY0 Buffer empty for TX buffer PHY0...
Page 72: Timestamp Config Register 6.7
7.4.5 Timestamp Config Register 6.7 The Timestamp Configuration register is used to configure the framer unit and is used to select which register of the timestamp memory is read. Name Description Mode Default 15:8 Reserved, write as 0, ignore on read DISREGARD_O 0: Do not overwrite timestamp LDEST_TIMES...
Page 73 A timestamp set is combined of the timestamp itself, the source port identity and the sequence ID stored in a 192 bit wide register. This is organized as shown below: Name Description Mode Default 191:176 MESSAGE_ID Message Type of the Undefined received message 001: PTP Sync message...
Page 74: Ptp_Config_N Register 6.9 / 6.13
7.4.2 PTP_CONFIG_n Register 6.9 / 6.13 The PTP Config register is used to configure the framer unit. There is one PTP config register for each PHY. The config register for PHY 0 is located at address 6.9, for PHY1 at 6.13. Name Description Mode...
Page 75 (transparent clock peer-to- peer mode) MODE_RX Set the PTP mode for RX 00: BC_PTP_V1 (boundary clock mode) 01: BC_PTP_V2 (boundary clock mode) 10: TC_E2E_PTP_V2 (transparent clock endto-end mode) 11: TC_P2P_PTP_V2 (transparent clock peer-to- peer mode) The following table gives an overview on how the different telegram types are handled depending on the configuration.
Page 76: Phy_Delay_Tx_N Register 6.11 / 6.15
RX Path: OC/BC OC/BC OC/BC OC/BC TC E2E TC P2P Frame type E2E/P2P E2E/P2P Step Step Step Step Step Step Sub TS Sub TS from Cor. from Cor. Sync Store TS Store TS Store TS Store TS field, Field Store TS Store TS FollowUp Sub TS...
Page 77 Name Description Mode Default 15:0 PHY_DELAY_ Value in ns by which RX_PORT_n timestamps taken for the PHYn on the RX side are corrected. R19UH0083ED0100 User Manual...
Page 78: Input Capture Unit
7.5 Input Capture Unit The input capture unit can be used to timestamp events on any of the GPIO pins. The timestamps are stored in a special memory area which can be accessed through the SMI via dedicated registers. The memory is configured as a FIFO structure;...
Page 79: Input Event Control Register 7.12
7.5.1 Input Event Control Register 7.12 The Input Event Control register is used to configure the input event unit. Name Description Mode Default ALL_PTR_RES Reset all pointers Reserved, ignore on read, write as 0 READ_WORD_NEXT 1: Reading next word, when accessing Read Register 0: No impact OVRRUN_ANY_GPIO...
Page 80: Input Capture Pin Control Register 7.8
7.5.2 Input Capture Pin Control register 7.8 The Input Capture Pin Control register is used to enable time-stamping for GPIO 0 to 7 and is used to configure the edge on which it should trigger. Name Description Mode Default 15:14 IN_CAP_GPIO7 00: Disable event timestamping for GPIO7 01: Timestamp on rising edge...
Page 81: Input Capture Pin Control Register 7.9
7.5.3 Input Capture Pin Control register 7.9 The Input Capture Pin Control register is used to enable timestamping GPIO 8 to 15and is used to configure the edge on which it should trigger. Name Description Mode Default 15:14 IN_CAP_GPIO15 00: Disable event timestamping for GPIO15 01: Timestamp on rising edge 10: Timestamp on falling edge...
Page 82: Input Capture Pin Control Register 7.10
7.5.4 Input Capture Pin Control register 7.10 The Input Capture Pin Control register is used to enable time-stamping for GPIO 16 to 19 and is used to configure the edge on which it should trigger. Name Description Mode Default 15:8 Reserved IN_CAP_GPIO19 00: Disable event timestamping...
Page 83: Input_Event_Data_Read_Word Register 7.15
7.5.5 INPUT_EVENT_DATA_READ_WORD Register 7.15 The INPUT_EVENT_DATA_READ_WORD register gives access to the stored timestamps. To read the complete timestamp the register has to be accessed six times. The least significant word is read first. The location of the data is as follows: Name Description...
Page 84: Input_Event_Data_Block_Read Register 7.14
7.5.6 INPUT_EVENT_DATA_BLOCK_READ Register 7.14 Name Description Mode Default 15:0 TIMESTAMP_ Returns the least significant READ_ BLOCK word (bits 15:0) of the next timestamp 7.5.7 INPUT_CAPTURE_DATA_POINTER Register 7.13 Name Description Mode Default 14:8 FILLING_LEVEL Number of data sets in memory 0: Event memory is empty 64: Event memory is full TIMESTAMP_ Value of the pointer to the...
Page 85: Pulse Generator Unit
7.6 Pulse Generator Unit The device has three pulse generator units which can generate pulses or events based on the PTP timer. Each can run in either of two different modes: single- shot or continuous pulse generation. A pulse is triggered when the START_TIME exceeds the time from the PTP timer. Although the START_TIME has a resolution of 1/32 ns, the exact output time may be up to 8 ns later as the output signal is running on the 125 MHz clock.
Page 86: Pulse Output Control Register 7.16
7.6.1 Pulse Output Control Register 7.16 The Pulse Output Control register controls the pulse units. All data written is stored for the channel selected in PULSE_CHANNEL. Name Description Mode Default 15:8 Reserved, write as 0, ignore on read LATCH_WIDTH Latch newly-written data from PULSE_WIDTH register and use for the next pulse.
Page 87: Pulse_Starttime Register 7.17
01: Single shot 10: Continuous 11: Reserved PULSE_ 000: Values in bits 9:3 and CHANNEL respective shadow registers PULSE_STARTTIME, PULSE_WIDTH and PULSE_INTERVAL will be written to channel 0 001: Values in bits 9:3 and respective shadow registers will be written to channel 1 010: Values in bits 9:3 will be written to channel 2 7.6.2 PULSE_STARTTIME Register 7.17...
Page 88: Pulse_Width Register 7.19
7.6.3 PULSE_WIDTH Register 7.19 Name Description Mode Default 47:38 PULSE_ Pulse high width seconds for WIDTH_SEC single and continuous pulse. The shortest pulse width value is 24 ns. 37:5 PULSE_ Pulse high width nanoseconds WIDTH_NS for single and continuous pulse. The shortest pulse width value is 24 ns.
Page 89: Electrical Characteristics
Electrical Characteristics 8.1 AC Timing 8.1.1 Serial Management Interface (SMI) Timing T1.1 MDIO read T1.2 T1.3 Valid data MDIO write Figure 1: SMI Timing ara- Description Units Notes meter T1.1 MDC to MDIO Data output delay from PHY T1.2 MDC to MDIO setup T1.3 MDC to MDIO...
Page 90: Reset Timing
8.1.2 Reset Timing T2.1 RESETB T2.2 T2.3 Strap pin latch *1） T2.4 DR (Device Ready) T2.5 Register access *2） Available Not available Figure 2: Reset Timing Para- Description Units Notes meter T2.1 RESETB pulse width T2.2 Strap input setup to RESETB rising T2.3 Strap input hold...
Page 91: Clock Timing
8.1.3 Clock Timing Para- Description Units Notes meter Reference clock frequency RMII (25MHz / 50 selectable) Clock -100 frequency tolerance *1) Duty cycle Jitter tolerance ps (rms)*1) *1) Root Mean Square R19UH0083ED0100 User Manual...
Page 92: 100Base-Tx Timings
8.1.4 100Base-TX Timings 8.1.4.1 100M MII Receive Timing RXD± IDLE J1 J0 K1 K0 PnRXCLK PnRXD [3:0] PnRXDV PnRXERR T3.1 T3.2 Figure 3: 100BT MII receive timing Para- Description Units Notes meter T3.1 Received signals output delay after rising edge of PnRXCLK T3.2 Start of RX-bit...
Page 93 8.1.4.2 100M MII Transmit Timing TXD±- IDLE J4 J3 J2 J1 J0 K4 K3 K2 K1 K0 D XCLK0 PnTXCLK Valid data PnTXD [3:0] PnTXEN PnTXERR T4.1 T4.2 T4.4 T4.3 T4.5 Figure 4: 100BT MII Transmit Timing Para- Description Units Notes meter T4.1...
Page 94: 10Base-T Timings
8.1.5 10Base-T Timings 8.1.5.1 10M MII Receive Timing PnRXCLK PnRXD[3:0] PnRXDV PnRXERR T5.1 Figure 5: 10BT MII receive timing Para- Description Units Notes meter T5.1 Received signals output delay after rising edge of P*RXCLK PnRXCLK frequency PnRXCLK duty-cycle R19UH0083ED0100 User Manual...
Page 95 8.1.5.2 10M MII Transmit Timing PnTXCLK Valid data PnTXD[3:0] PnTXEN PnTXERR T6.1 T6.2 Figure 6: 10BT MII transmit timing Para- Description Units Notes meter T6.1 Transmit signals setup to falling edge of PnTXCLK T6.2 Transmit signals hold to falling edge of PnTXCLK PnTXCLK frequency...
Page 96: Rmii 10/100Base-Tx Timings
8.1.6 RMII 10/100Base-TX Timings 8.1.6.1 RMII Receive Timing CLK50MHz PnRXD[1:0] P0CRS_DV T7.1 Figure 7: RMII receive timing Para- Description Units Notes meter T7.1 Receive signals output delay after rising edge of CLK50MHz CLK50MHz frequency *1) External 50MHz clock input R19UH0083ED0100 User Manual...
Page 97 8.1.6.2 RMII Transmit Timing CLK50MHz Valid PnTXD[1:0] PnTXEN data T8.1 T8.2 Figure 8: RMII transmit timing Para- Description Units Notes meter T8.1 Transmit signals setup to rising edge of CLK50MHz T8.2 Transmit signals hold after rising edge of CLK50MHz CLK50MHz frequency *1) External 50MHz clock input R19UH0083ED0100...
Page 98: Sequence For Turn On
8.1.7 Sequence for turn on RESETB must be released after all external power is ready. Crystal/Clock ALL External Power resetb RESETB Figure 9: Reset timing  Paramet Description Units Notes Power on Reset timing R19UH0083ED0100 User Manual...
Page 99: Dc Characteristics
8.10 DC Characteristics 8.10.1 Absolute Maximum Ratings Parameter Symbol Conditions Rating Units Analogue power P1VDDMEDIA, -0.5 to +2.0 supply voltage P2VDDMEDIA, VDDAPLL Digital Power Supply VDD15 -0.5 to +2.0 Voltage I/O Voltage VDDIO -0.5 to +4.6 Analog 3.3V power VDDACB -0.5 to 4.6 supply Analog 3.3V power...
Page 100: Recommended Operating Conditions
8.10.2 Recommended Operating Conditions Parameter Symbol Conditions Rating Units Analogue power P1VDDMEDIA, 1.425 to supply voltage P2VDDMEDIA, 1.575 VDDAPLL Digital Power Supply VDD15 1.425 to Voltage 1.575 I/O Voltage VDDIO 2.25 to 2.75 3.0 to 3.6 Analog 3.3V power VDDACB 3.0 to 3.6 supply Analog 3.3V power...
Page 101: Dc Electrical Characteristics
8.10.3 DC Electrical Characteristics Parameter Symbol Conditions Unit External 3.3V Current 100B 1.5V Consumption supplied 1.5V Internal 3.3V Regulater used 1.5V External 3.3V 1.5V supplied 1.5V Internal 3.3V Regulater 1.5V used Internal pull up  stru 14.2 31.9 80.7 Ω strap resistor Internal pull down ...
Page 102: 100Base-Fx Output Characteristics
8.10.5 100Base-FX Output Characteristics Conditio Parameter Symbol Units Output Voltage - Low [V] -1.81 -1.55 Vol-VDDIO Output Voltage - High [V] -1.12 -0.88 Voh-VDDIO R19UH0083ED0100 User Manual...
Page 103 Physical dimensions R19UH0083ED0100 User Manual...
Page 104 Revision history Date Revision Changes March 19, 2013 1.00 Initial release R19UH0083ED0100 User Manual...
Page 105 Industrial Ethernet R19UH0083ED0100 User Manual...

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