Seco CCHPC-C78-C User Manual page 42

Description
+12V Power Rail
+12V Power Rail
+12V Power Rail
Power Ground
SM Bus Clock line. +3.3V_RUN electrical level with
up resistor, derived by SMB_CK with
mosfet voltage level converter
SM Bus Data line. +3.3V_RUN electrical level with
up resistor, derived by SMB_DAT with
mosfet voltage level converter
Power Ground
+3.3V Power Rail
Not Connected
+3.3V Auxiliary Power Rail
Wake signal for link reactivation
Not Connected
Power Ground
PCI-e Transmitter lane 4+
PCI-e Transmitter lane 4-
Power Ground
Hot Plug presence detect. Input Signal from add in
card used to enable the reference clock of this slot.
Active low signal, +3.3V_RUN electrical level with a
10k
Power Ground
PCI-e Transmitter lane 5+
CCHPC-C78-C
CCHPC-C78-C - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.O. - Reviewed by E.S. Copyright © 2023 SECO S.p.A.
PCI-e x 4 Slot CN74
Pin name Pin nr. Pin nr.
+12V_RUN B1 A1
+12V_RUN B2 A2
+12V_RUN B3 A3
GND B4 A4
PCIE_ SMB_CLK B5 A5
PCIE_ SMB_DAT B6 A6
GND B7 A7
+3.3V_RUN B8 A8
JTAG1 B9 A9
+3.3V_ALW B10 A10
WAKE0# B11 A11
RSVD B12 A12
GND B13 A13
PCIE_TX4+ B14 A14
PCIE_TX4- B15 A15
GND B16 A16
PRSNT2# B17 A17
GND B18 A18
PCIE_TX5+ B19 A19
Pin name Description
PRSNT1# Hot Plug presence detect (tied to GND)
+12V_RUN +12V Power Rail
+12V_RUN +12V Power Rail
GND Power Ground
JTAG2 Not connected
Not connected
JTAG3
JTAG4 Not connected
JTAG5 Not connected
+3.3V_RUN +3.3V Power Rail
+3.3V_RUN +3.3V Power Rail
Reset signal to the add-in card, derived by
CB_RESET# using a Ultra High Speed CMOS
PCIEx4_2_RST#
buffer. Active low signal, +3.3V_ALW electrical level
with a 100k
GND Power Ground
PCI-e reference clock lane +, derived by
PCIEx4_2_CLK_P
PCIE_CK_REF+ using a Clock Buffer
PCI-e reference clock lane +, derived by
PCIEx4_2_CLK_N
PCIE_CK_REF- using a Clock Buffer
GND Power Ground
PCIE_RX4+ PCI-e Receiver lane 4+
PCIE_RX4- PCI-e Receiver lane 4-
GND Power Ground
RSVD Not Connected
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