Analog Devices ADM1063 Manual page 6

ADM1063
Parameter
4
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Bus Free Time, t
BUF
Start Setup Time, t
SU;STA
Stop Setup Time, t
SU;STO
Start Hold Time, t
HD;STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
R
SCL, SDA Fall Time, t
F
Data Setup Time, t
SU;DAT
Data Hold Time, t
HD;DAT
Input Low Current, I
IL
SEQUENCING ENGINE TIMING
State Change Time
1
At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2
All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured.
3
Specification is not production tested but is supported by characterization data at initial product release.
4 Timing specifications are guaranteed by design and supported by characterization data.
Min Typ Max
400
1.3
0.6
0.6
0.6
1.3
0.6
300
300
100
5
1
10
Rev. C | Page 6 of 32
Unit Test Conditions/Comments
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
μA V = 0 V
IN
μs