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(with MPC5567 extension) Hardware Manual Edition December 2008 A product of a PHYTEC Technology Holding company Arrow.com. Downloaded from...
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PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.
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Block Diagram phyCORE-MPC5554........6 Figure 2: Top View of the phyCORE-MPC5554 Revision 1239.3... 7 Figure 3: Bottom View of the phyCORE-MPC5554 Revision 1239.3 ..8 Figure 4: Pinout of the phyCORE-MPC5554 (Bottom View) ....10 Figure 5: Numbering of the Jumper Pads..........24...
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Signal Pin Assignment for the phyCORE-MPC5554 / Development Board / Expansion Board ........80 Table 17: Pin Assignment Power Supply for the phyCORE-MPC5554 / Development Board / Expansion Board ........81 Table 18: Signal Pin Assignment for the phyCORE-MPC5567 / Development Board / Expansion Board ........
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The phyCORE-MPC5554 is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports...
The phyCORE-MPC5554 is a subminiature (84 x 57 mm) insert-ready Single Board Computer populated with Freescale's PowerPC MPC5554 microcontroller. Its universal design enables its insertion in a wide range of embedded applications.
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The phyCORE-MPC5554 offers the following features: • Single Board Computer in subminiature form factor (84 x 57 mm) according to phyCORE specifications •...
We recommend connecting all available +3V3 and +5 V input pins to the power supply system on a custom carrier board housing the phyCORE-MPC5554 and at least the matching number of DGND pins neighboring the +3V3 and +5 V pins.
As Figure 4 indicates, all controller signals extend to surface mount technology (SMT) connectors (0.635 mm) lining two sides of the module (referred to as phyCORE-connector; refer to section 12). This allows the phyCORE-MPC5554 to be plugged into any target application like a "big chip". Figure 4:...
3 Jumpers For configuration purposes, the phyCORE-MPC5554 has 37 solder jumpers, some of which have been installed prior to delivery. Figure 5 illustrates the numbering of the jumper pads, while Figure 6 and Figure 7 indicate the location of the jumpers on the board.
4 Power Requirements The phyCORE-MPC5554 must be supplied with two different supply voltages: +3.3 V ± 5 % with 1A ** Supply voltage VDD3V3 Pins at Connector X2 1C, 2C, 1D, 2D, 4D, 5D +5 V ± 10 % with 100mA **...
System Start-Up Configuration The phyCORE-MPC5554 supports four different software start-up modes: • Internal Flash Memory • External Memory controlled by /CS0 • SCI UART • FlexCAN Internal/External Memory Boot The decision which mode is used after /RESET goes from active to inactive state is defined by the external signal /RSTCFG (X2C9).
6.1 External Standard Flash Memory (U3, U4) The Flash memory devices used on the phyCORE-MPC5554 operate in 16-bit mode and are organized in 32-bit data bus with. The device at U3 connects to the low data bus while device U4 connects to the high data bus.
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System Memory Use of Flash memory enables in-circuit programming of the module. The Flash devices on the phyCORE-MPC5554 are programmable at 3.3 VDC. Consequently, no dedicated programming voltage is required. As of the printing of this manual, Flash devices generally have a life expectancy of at least 100,000 erase/program cycles.
The memory is generally accessed via /CS1 without wait states. The phyCORE-MPC5554 can be populated with memory devices of various capacities. Generally, each memory bank can only be populated with memory devices of a consistent size. Solder jumper J19 is used to configure the memory capacity and pre-installed at time of delivery.
System Memory 6.3 Serial Memory (U15) The phyCORE-MPC5554 features a non-volatile memory device with a serial I C interface. This memory can be used for storage of configuration data or operating parameters, that must not be lost in the event of a power interruption. Depending on the module's configuration, this memory can be in the form of an EEPROM, FRAM or SRAM.
7 FPGA System Logic Device U21 The FPGA logic device U21, supplied by Lattice Semiconductor, is responsible for routing resources on the phyCORE-MPC5554 and provides a very flexibly way to connect and operate application- specific hardware components or interfaces in a target design. In...
FPGA Firmware Development A basic firmware project with pin and signal assignment is provided by PHYTEC. This project is written in VHLD and can easily be extended with customer-specific functionality. The required development tool is called ispLever and is provided by Lattice Semiconductor.
RS-232 transceiver located phyCORE-MPC5554 at U10. This device adjusts the signal levels of the TXDA/RXDA and TXDB/RXDB lines (MPC5554 eSCI UART). The RS-232 interface enables connection of the module to a COM port on a host-PC or other peripheral devices. In this instance, the...
CAN signals is required. For larger CAN bus systems, an external de-coupler device should be implemented to optically isolate the CAN transceiver and the phyCORE-MPC5554. To add external circuits for optical isolation, the CAN transceivers must be removed and the CAN bus signals bypassed by means of solder jumpers J30 and J31.
(X2) In order to connect a true Nexus port, an external 38-pin connector must be located on the customer application board. The PHYTEC phyCORE-MPC5554 Development Board (part number PCM-979) features such Nexus connector at X2 and can be used as an example.
LAN91c111 Ethernet Controller LAN91C111 Ethernet Controller Connection of the phyCORE-MPC5554 to the world wide web or a local network is possible if the optional LAN91C111 10/100 Mbit/s Ethernet controller populates the module at U20. This section only describes the functional characteristics of the LAN91C111 as implemented on the phyCORE-MPC5554.
IP number to the hardware's MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE-MPC5554 is located on the bar code sticker attached to the module.
24-hour format Automatic word address incrementing Programmable alarm, timer and interrupt functions If the phyCORE-MPC5554 is equipped with a battery (VBAT), the Real-Time Clock runs independently of the board’s power supply. The Real-Time Clock is programmed via the I C bus (address 0xA2 / 0xA3).
Development Board PCM-979 11 phyCORE Development Board PCM-979 PHYTEC Development Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start-up and subsequent communication to and programming of applicable PHYTEC Single Board Computer (SBC) modules. Development...
11.2.2 Jumpers on the phyCORE Development Board PCM-979 Peripheral components of the phyCORE Development Board PCM-979 can be connected to the signals of the phyCORE-MPC5554 by setting the applicable jumpers. The Development Board's peripheral components are configured for use with the phyCORE-MPC5554 by means of removable jumpers. If no jumpers are set, no signals are connected to the DB-9 connectors, the control and display units or the CAN transceivers.
Development Board PCM-979 supported by the phyCORE-MPC5554 and appropriate jumper settings to activate these components. Depending on the specific configuration of the phyCORE-MPC5554 module, alternative jumper settings can be used. These jumper settings are different from the factory default settings as shown in Figure 13 and enable alternative or additional functions on the phyCORE Development Board PCM-979 depending on user needs.
Plug P1A is the bottom plug of the double DB-9 connector at P1. P1A is connected to the first FlexCAN interface (FlexCAN A) of the phyCORE-MPC5554 via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following two configurations are possible: 1.
Plug P1B is the upper plug of the double DB-9 connector at P1. P1B is connected to the second FlexCAN interface (FlexCAN B) of the phyCORE-MPC5554 via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible: 1.
The phyCORE Development Board PCM-979 offers a programmable LED at D6 for user implementations. This LED can be connected to port pin EMIOS0 of the phyCORE-MPC5554 which is available with JP7 = closed. A low-level at port pin EMIOS0 causes the LED to illuminate, LED D6 remains off when writing a high-level to EMIOS0.
The pin assignment on the phyCORE-MPC5554, in conjunction with the expansion bus (X7) on the Development Board and the patch field on an expansion board, is as follows: 11.3.7.1 Pin Assignment for phyCORE-MPC5554 phyCORE-MPC5554 Development Board Expansion Board Expansion Bus...
Technical Specification 12 Technical Specifications The physical dimensions of the phyCORE-MPC5554 are represented in Figure 24. Figure 24: Physical Dimensions (Top View) The holes with diameter 0.7 m and 0.9 mm are the positioning holes for the Molex connectors. The module edge mounting holes are plated and connected to DGND.
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Two different heights are offered for the receptacle sockets that correspond to the connectors populating the underside of the phyCORE-MPC5554. The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board. In order to get the exact spacing, the maximum component height (3 mm) on the underside of the phyCORE must be subtracted.
Alternatively, a hot air gun can be used to heat and loosen the bonds. Integrating the phyCORE-MPC5554 in Application Circuitry Successful integration in user target circuitry depends on whether the layout for the GND connections matches those of the phyCORE module.
Data line D31 represents the LSB and D0 the MSB. Address line A31 represents the LSB and A8 the MSB. Byte ordering is big Endian. Due to the conversion of little to big Endian byte ordering, the byte portions of LAN91C111 data bus are swapped to the MPC5554 data bus.
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