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Phytec phyCORE-LPC3250 Hardware Manual

System on module and carrier board
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phyCORE-LPC3250
System on Module and Carrier Board
Hardware Manual
Document No:
L-714e_1
Product No:
PCM-040
SOM PCB No:
1304.1
CB PCB No:
1305.2, 1305.3
Edition:
January 27, 2009
A product of a PHYTEC Technology Holding Company

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Summary of Contents for Phytec phyCORE-LPC3250

  • Page 1 System on Module and Carrier Board Hardware Manual Document No: L-714e_1 Product No: PCM-040 SOM PCB No: 1304.1 CB PCB No: 1305.2, 1305.3 Edition: January 27, 2009 A product of a PHYTEC Technology Holding Company...

  • Page 2: Table Of Contents

    Part I: PCM-040/phyCORE-LPC3250 System on Module ........
  • Page 3 Part II: PCM-967/phyCORE-LPC3250 Carrier Board........

  • Page 4: List Of Tables

    Part I: PCM-040/phyCORE-LPC3250 System on Module ........
  • Page 5 Table 50-1. Revision History ........... 127 © PHYTEC America LLC 2009...
  • Page 6 Fig. 14-1. phyCORE-LPC3250 Physical Dimensions ........52...

  • Page 7: Conventions, Abbreviations And Acronyms

    Power sourcing equipment; the device in a PoE network that provides power to con- nected devices--usually a switch, router, or stand alone power injector. Real-time clock. Stage 1 Loader; the third level bootloader flashed on the phyCORE-LPC3250 SOM. Surface mount technology. © PHYTEC America LLC 2009...
  • Page 8 Conventions, Abbreviations and Acronyms L-714e_1 Table 1-1. Abbreviations and Acronyms used in this Manual (Continued) Abbreviation Definition System on Module; used in reference to the PCM-040/phyCORE-LPC3250 System on Module. VBAT SOM battery supply input Vector floating point. © PHYTEC America LLC 2009...

  • Page 9: Preface

    PHYTEC System on Modules (SOMs) are designed for installation in electrical appliances or, combined with the PHYTEC Carrier Board, can be used as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

  • Page 10: Part I: Pcm-040/Phycore-Lpc3250 System On Module

    PCM-040/phyCORE-LPC3250 System on Module L-714e_1 Part I: PCM-040/phyCORE-LPC3250 System on Module Part 1 of this 3 part manual provides detailed information on the phyCORE-ARM9/LPC3250 System on Module (SOM) designed for custom integration into customer applications. The information in the following chapters is applicable to the 1304.1 PCB revision of the phyCORE- LPC3250 SOM.

  • Page 11: Introduction

    Microvias are used on the boards, providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design. The phyCORE-LPC3250 is a sub-miniature (70 x 58 mm) insert-ready SOM populated with the NXP LPC3250 ARM926EJ-S core processor. Its universal design enables its insertion in a wide range of embedded applications.
  • Page 12 32-bit millisecond timer driven from the RTC clock • Processor based watchdog timer • 12x PWM outputs • JTAG interface for debugging and download of user code • Single supply voltage of 3.15V with on-board power management • Industrial temperature range (-40°...+85°) © PHYTEC America LLC 2009...

  • Page 13: Block Diagram

    Part I, Chapter 1: Introduction L-714e_1 1.1 Block Diagram Fig. 1-1. phyCORE-LPC3250 Block Diagram © PHYTEC America LLC 2009...

  • Page 14: View Of The Phycore-Lpc3250

    Part I, Chapter 1: Introduction L-714e_1 1.2 View of the phyCORE-LPC3250 Fig. 1-2. Top View of the phyCORE-LPC3250 (Controller Side) © PHYTEC America LLC 2009...

  • Page 15: Fig. 1-3. Bottom View Of The Phycore-Lpc3250 (Connector Side)

    Part I, Chapter 1: Introduction L-714e_1 Fig. 1-3. Bottom View of the phyCORE-LPC3250 (Connector Side) © PHYTEC America LLC 2009...

  • Page 16: Pin Description

    The upper left-hand corner of the numbered matrix (pin 1A) is thus covered with the corner of the phyCORE-LPC3250 marked with a white triangle. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.

  • Page 17: Table 2-1. Pin Descriptions, Phycore-Connector X2, Row A

    VCC_EMB Buffered µC signal D1 (memory bus data bit D1) b_D2 VCC_EMB Buffered µC signal D2 (memory bus data bit D2) b_D4 VCC_EMB Buffered µC signal D4 (memory bus data bit D4) Ground b_D7 VCC_EMB Buffered µC signal D7 (memory bus data bit D7) © PHYTEC America LLC 2009...
  • Page 18 µC signal LCD10 (green color bit) Ground LCD7 µC signal LCD7 (red color bit) LCD4 µC signal LCD4 (red color bit) LCD3 µC signal LCD3 (red color bit) LDC0 µC signal LCD0 (red color bit) © PHYTEC America LLC 2009...

  • Page 19: Table 2-2. Pin Descriptions, Phycore-Connector X2, Row B

    VCC_EMB Buffered µC signal A5 (memory bus address bit A5) b_A6 VCC_EMB Buffered µC signal A6 (memory bus address bit A6) b_A8 VCC_EMB Buffered µC signal A8 (memory bus address bit A8) Ground b_A11 VCC_EMB Buffered µC signal A11 (memory bus address bit A11) © PHYTEC America LLC 2009...
  • Page 20 µC signal LCD22 (blue color bit) Ground LCD18 µC signal LCD18 (blue color bit) LCD16 µC signal LCD16 (blue color bit) LCD15 µC signal LCD15 (green color bit) LCD12 µC signal LCD12 (green color bit) © PHYTEC America LLC 2009...

  • Page 21: Table 2-3. Pin Descriptions, Phycore-Connector X2, Row C

    Pin # Signal Description 3.15V 3.15V primary voltage supply input 3.15V 3.15V primary voltage supply input Ground VCC_SDIO SDIO controller voltage interface select 2.25 – 3.6V VCC_SDIO SDIO controller voltage interface select 2.25 – 3.6V © PHYTEC America LLC 2009...
  • Page 22 U3_DCD 3.15V µC signal U3_DCD/GPI_05 U6_IRTX 3.15V µC signal U6_IRTX I2C2_SCL 1.8V µC signal I2C2_SCL. This signal has an internal 2.2k pull-up. I2C1_SCL 3.15V µC signal I2C1_SCL. This signal has an internal 2.2k pull-up. Ground © PHYTEC America LLC 2009...
  • Page 23 SPI bootable EEPROM and has an inter- nal 10k pull-up. Ground I2STX_CLK1 3.15V µC signal I2STX_CLK1/MAT3.0 I2STX_SDA1 3.15V µC signal I2STX_SDA1/MAT3.1 I2STX_WS1 3.15V µC signal I2STX_WS1/CAP3.0 ENET_RXD2 3.15V µC signal ENET_RXD2/GPI_00 Ground ENET_CRS 3.15V µC signal ENET_CRS/KEY_COL3 © PHYTEC America LLC 2009...

  • Page 24: Table 2-4. Pin Descriptions, Phycore-Connector X2, Row D

    VCC_AD_EXT 3.15V µC ADC power supply input VCC_AD_EXT 3.15V µC ADC power supply input Not connected Not connected 3.15V Watchdog input. Connect this pin to an applicable sig- nal to periodically reset the watchdog timer. © PHYTEC America LLC 2009...
  • Page 25 Ethernet positive differential transmit output Note ENET_CLKEN 3.15V Ethernet clock enable. This pin has an internal 100k pull-up. Ground this pin to disable the ethernet clock. Typically this is used in a low power mode. © PHYTEC America LLC 2009...
  • Page 26 ENET_RXD0 3.15V µC signal ENET_RXD0/KEY_COL4 ENET_TXD2 3.15V µC signal ENET_TXD2/KEY_ROW1 ENET_TXD1 3.15V µC signal ENET_TXD1/KEY_ROW5 TST_CLK2 3.15V µC signal TST_CLK2 Ground /SDIO_WP VCC_SDIO SDIO controller write protect input. This pin has an internal 100k pull-up. © PHYTEC America LLC 2009...
  • Page 27 Analog ground ADIN2 3.15V µC signal ADIN2 a. 3.0V is the standard phyCORE-LPC3250 SOM configuration. b. Typical -- see ADM3307 datasheet for details. c. See the LAN8700I datasheet for details. d. See the ISP1301 datasheet for details. © PHYTEC America LLC 2009...

  • Page 28: Jumpers

    Part I, Chapter 3: Jumpers L-714e_1 3 Jumpers For configuration purposes, the phyCORE-LPC3250 has 24 solder jumpers, some of which have been installed prior to delivery. Figure 3-1 Figure 3-2 indicate the location of the solder jumpers on the board. There are 11 solder jumpers located on the top side of the module (opposite side of connectors) and 13 solder jumpers on the bottom side.

  • Page 29: Table 3-1. Jumper Settings

    Data bus buffer D0...7 output enable controlled by processor signal BLS0. Data bus buffer D0...7 output permanently enabled. Data bus buffer D8...15 output enable controlled by processor sig- nal BLS1. Data bus buffer D8...15 output permanently enabled. © PHYTEC America LLC 2009...
  • Page 30 Voltage regulator U23 supplies VCC_CORE power. J28 0R Open Voltage regulator U23 disconnected from VCC_1V2. 4.5.1 Closed Voltage regulator U23 supplies VCC_1V2 power. J29 0R Open Voltage regulator U27 disconnected from VCC_CORE. 4.5.2 Closed Voltage regulator U27 supplies VCC_CORE power. © PHYTEC America LLC 2009...

  • Page 31: Fig. 3-3. Default Jumper Settings (Controller Side)

    SPI EEPROM write protected. J32 0R Off-chip RTC power is automatically selected between VCC and VBAT based on VCC presence. Off-chip RTC power is powered by VBAT input only. Fig. 3-3. Default Jumper Settings (Controller Side) © PHYTEC America LLC 2009...

  • Page 32: Fig. 3-4. Default Jumper Settings (Connector Side)

    Part I, Chapter 3: Jumpers L-714e_1 Fig. 3-4. Default Jumper Settings (Connector Side) © PHYTEC America LLC 2009...

  • Page 33: Power

    1.8V, and 1.2V, and adjustable 0.9-1.2V voltage supplies required by the LPC3250 MCU and on-board components from the primary 3.15V supplied to the SOM. For proper operation the phyCORE-LPC3250 must be supplied with a voltage source of 3.15V ± 0.1V at the VCC pins on the phyCORE-Connector X2. See Table 2-1 for VCC pin locations.

  • Page 34: Sdio Controller Power (Vcc_Sdio)

    3.15V the VCC_SDIO pins can be connected directly to the VCC power supply and the SDIO_POW0/1 pins can be left unconnected. 4.5 On-board Voltage Regulators The phyCORE-LPC3250 provides three on-board switching regulators to source the 1.2V, 1.8V, and adjustable 0.9-1.2V voltages required by the processor and on-board components. Figure 4-1 presents a graphical depiction of the powering scheme.

  • Page 35: Primary 1.2V And 1.8V Supplies (U23)

    1.8V 1.2V 1.8V Fig. 4-1. phyCORE-LPC3250 On-board Powering Scheme 4.5.1 Primary 1.2V and 1.8V Supplies (U23) The dual output switching regulator located at U23 generates the 1.2V and 1.8V core and peripheral supplies required by system components from the primary VCC = 3.15V board supply. Various jumpers have been provided as current measurement access points on the outputs of both of these supplies.

  • Page 36: Adjustable Core Voltage Supply (U27)

    If the shunt resistor is too large the voltage at the output could be below the supervisor reset threshold and force the system into reset. A good starting place is a 0.025 Ohm precision shunt in a 0805 package. © PHYTEC America LLC 2009...

  • Page 37: Voltage Supervisor (U16, U17)

    L-714e_1 4.6 Voltage Supervisor (U16, U17) The phyCORE-LPC3250 comes equipped with two triple voltage supervisor IC's located at U16 and U17. These voltage supervisors are responsible for monitoring all on-board supply voltages (with the exception of the adjustable core supply voltage which is not monitored) and issuing a system reset during a power- up, power-fail, or power-down event.
  • Page 38 To prevent this from happening external sleep circuitry should be used which remembers the sleep state and is reset via the /RESET_BAT signal should a sleep supply (VBAT, VCC_RTC, VCC_SDRAM) fail. © PHYTEC America LLC 2009...

  • Page 39: Deep Sleep

    Under normal operating conditions S1 will be closed and the system will be powered up. The user will initiate a sleep event by pressing the Power Button. The phyCORE-LPC3250 will detect the press of the power button and begin a sleep sequence in software preparing the system for the removal of primary power.
  • Page 40 RTC and SDRAM domains are powered by the VCC supply. See the Texas Instruments TPS2115 battery switch datasheet for more details. For a detailed explanation of the sleep control circuitry on the phyCORE-LPC3250 Carrier Board see Chapter © PHYTEC America LLC 2009...

  • Page 41: External Rtc (U26)

    RTC. This RTC provides a secondary time keeping source, along with a secondary alarm mechanism to the processor via the /RTC_INT signal. By default the /RTC_INT signal is used on the phyCORE-LPC3250 Carrier Board to wake-up the power system during a deep sleep.

  • Page 42: External Watchdog

    2-1) must be taken out of Hi-Z. When the phyCORE-LPC3250 SOM is mounted on the phyCORE-LPC3250 Carrier Board the watchdog can be taken out of Hi-Z by closing an applicable jumper. See the phyCORE-LPC3250 Carrier Board Chapter 38 for details on the jumper and associated settings. When closed processor signal GPO_20 is connected to the WDI input of the watchdog circuit.

  • Page 43: System Configuration And Booting

    The boot mode is controlled by strapping the SERVICE_N signal of the processor HIGH or LOW after a reset. On the phyCORE-LPC3250 this signal is labeled as /SERVICE. An on-board pull-up resistor pulls this signal HIGH. However, when installed on the phyCORE-LPC3250 Carrier Board the default boot configuration jumper connects the /SERVICE signal to GND.
  • Page 44 ROM can only copy code from block 0 or block 1, this limits the size of the secondary boot loader to be constricted to stay within a single block in NAND Flash. For the phyCORE-LPC3250 NAND Flash this limit is 16kBytes. In practice this is limited to 15.5kBytes for reasons which will become apparent in the sections that follow.

  • Page 45: Fig. 8-1. Small Page Slc Nand Flash Structure

    0 bad block information. This information is needed by the LPC3250 boot ROM to find out what type of NAND Flash the controller will be interfacing, how much code to copy from NAND © PHYTEC America LLC 2009...

  • Page 46: Stage 1 Loader

    Linux or WinCE. To simplify and enhance the boot process the phyCORE-LPC3250 comes pre-flashed with a special boot loader written by NXP. This boot loader, called the "Stage 1 Loader" is discussed in more detail in the follow section.

  • Page 47: Boot Sequence

    In addition to the help menus NXP has published a document detailing the Kickstart Loader and the Stage 1 Loader. Please refer to this document, located on your PHYTEC Spectrum CD in PHYTEC\phyCORE- LPC3250\Documentation\Stage1 Loader, for more information regarding these boot loaders.

  • Page 48: System Memory

    4. EEPROM (U9): from 1KB to 32KB The following sections of this chapter detail each memory type used on the phyCORE-LPC3250 SOM. 9.1 SDRAM (U10, U11) The phyCORE-LPC3250 comes pre-configured with 16, 32 or 64MB of 133MHz SDR SDRAM configured for 32-bit access using two 16-bit wide RAM chips at U10 and U11.

  • Page 49: Nor Flash (U12, U13)

    Part I, Chapter 9: System Memory L-714e_1 Refer to the NXP Common Driver Library (CDL) provided on the PHYTEC Spectrum CD for code examples for accessing the NAND Flash. It should be noted that the NAND Flash has a dedicated memory bus on the LPC3250 to the NAND device.

  • Page 50: Table 9-4. Eeprom Configuration Struct Dramcfg Field Format

    Set this jumper to the 2+3 position to maintain control over write protection. In addition to this jumper particular internal EEPROM status register bits must be configured to enable full write protection. See the Atmel AT25256AN datasheet for details. © PHYTEC America LLC 2009...

  • Page 51: Memory Map

    9.6 Memory Map The phyCORE-LPC3250 memory map is summarized in Table 9-6 below. Make note of the memory addresses assigned to functions on the phyCORE-LPC3250. Namely these are the SDIO controller, NOR Flash, and SDRAM. Table 9-6. phyCORE-LPC3250 Memory Map Address...

  • Page 52: Serial Interfaces

    TTL levels. 10.2 Ethernet PHY (U6) The phyCORE-LPC3250 comes populated with an SMSC LAN8700I Ethernet PHY at U6 supporting 10/ 100 Mbps Ethernet connectivity. The PHY uses an RMII interface to the Ethernet MAC integrated on the LPC3250.

  • Page 53: Configuring The Phy Operating Mode (J7, J8, J9)

    R22, R23, R24, R126. In addition the Ethernet clock oscillator must be disabled by driving the ENET_CLKEN signal LOW. This can be accomplished by installing the applicable jumper on the phyCORE-LPC3250 Carrier Board. See Chapter 25 for details on this jumper and its configuration. See Figure 10-1 for the location of the resistors that must be removed for keyboard operation.

  • Page 54: Usb Otg Transceiver (U24)

    PSW signal is connected to the power supply enable input pin and the USB_VBUS signal is connected to the 5V power supply output. See the phyCORE-LPC3250 Carrier Board schematics for reference circuitry that makes use of the USB_ADR/PSW pin to provide additional host current. The USB_ADR/PSW pin is pulled-down on the SOM by default.

  • Page 55: Table 10-3. Applicable Usb Operating Mode Connectors

    Part I, Chapter 10: Serial Interfaces L-714e_1 In addition to optional power control circuitry via the USB_ADR/PSW signal, an external USB connector is all that is needed to interface the phyCORE-LPC3250 USB functionality. Table 10-3 details applicable connectors for various end application operating modes. The applicable interface signals (USB_D+/...

  • Page 56: Sdio Controller (U14)

    Part I, Chapter 11: SDIO Controller (U14) L-714e_1 11 SDIO Controller (U14) The phyCORE-LPC3250 comes populated with the NXP SDIO101 SD/SDIO/MMC/CE-ATA compliant host controller at U14. The SDIO controller provides the hardware compliant layer to SD, SDIO, MMC, and CE- ATA enabled devices.

  • Page 57: Table 11-2. Sdio Controller Interface Signals

    It should be noted that the GPI_7 interrupt signal has an internal 10k pull-up on-board. The SDIO reset signal is connected through an inverter to the phyCORE-LPC3250 /RESET_EMB signal. This will trigger a SDIO reset during power-up, power-fail, and power-down events.

  • Page 58: Debug Interface (X1)

    Figure 12-1 below for details. Fig. 12-1. JTAG Interface X1 (Controller Side) The JTAG edge card connector X1 provides an easy means of debugging the phyCORE-LPC3250 in your target system via an external JTAG probe, such as the Abatron BDI2000. NOTE: The JTAG connector X1 only populates phyCORE-LPC3250 modules with order code PCM-040-xxxxxD.

  • Page 59: Bus Buffers (U1, U2, U3, U4, U5)

    L-714e_1 13 Bus Buffers (U1, U2, U3, U4, U5) The phyCORE-LPC3250 provides a buffered version of the processor's external memory bus via bus buffers U1, U2, U3, U4 and U5 for connection of external memory mapped peripherals. Data bus direction is controlled by the processors output enable signal /OE.

  • Page 60: Buffered Memory Bus Voltage Select (J21)

    To interface 1.8V low power devices to the external memory bus J21 should be set to the 1+2 position. WARNING: The standard phyCORE-LPC3250 configuration does not allow a 1.8V external memory bus voltage. The on-board NOR flash and SDIO controller are only operable at 3.15V. The 1.8V setting should not be used unless you have specifically ordered a configuration that is compatible to 1.8V.

  • Page 61: Technical Specifications

    Part I, Chapter 14: Technical Specifications L-714e_1 14 Technical Specifications The physical dimensions of the phyCORE-LPC3250 are represented in Figure 14-1. The module's profile is approximately 7.9mm thick, with a maximum component height of approximately 3.35mm on the bottom (connector) side of the PCB and approximately 2.58mm on the top (microcontroller) side. The board itself is approximately 1.26mm thick.

  • Page 62: Table 14-2. Static Operating Characteristics

    VBAT should always be less than VCC for proper operation. c. Operating limits are per the NXP LPC3250 datasheet for the VCCA(3V0) pins. These specifications describe the standard configuration of the phyCORE-LPC3250 as of the printing of this manual.

  • Page 63: Hints For Handling The Phycore-Lpc3250

    Part I, Chapter 15: Hints for Handling the phyCORE-LPC3250 L-714e_1 15 Hints for Handling the phyCORE-LPC3250 Removal of various components, such as the microcontroller and the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board as well as surrounding components and sockets remain undamaged while de-soldering.

  • Page 64: Component Placement Diagrams

    Part I, Chapter 16: Component Placement Diagrams L-714e_1 16 Component Placement Diagrams Fig. 16-1. phyCORE-LPC3250 Component Placement (Controller Side) © PHYTEC America LLC 2009...

  • Page 65: Fig. 16-2. Phycore-Lpc3250 Component Placement (Connector Side)

    Part I, Chapter 16: Component Placement Diagrams L-714e_1 Fig. 16-2. phyCORE-LPC3250 Component Placement (Connector Side) © PHYTEC America LLC 2009...

  • Page 66: Part Ii: Pcm-967/Phycore-Lpc3250 Carrier Board

    SOM is deployed. Carrier Board schematics with BoM are available under a Non Disclosure Agreement (NDA). Re-use of Carrier Board circuitry likewise enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

  • Page 67: Introduction

    PHYTEC System on Module (SOM). Carrier Boards are designed for evaluation, testing and prototyping of PHYTEC SOMs in laboratory environments prior to their use in customer designed applications.

  • Page 68: Overview Of Peripherals

    Ref. Des. Description Chapter phyCORE-Connector for phyCORE-LPC3250 SOM connectivity GPIO expansion connector. Most phyCORE-LPC3250 signals are made avail- able at this connector. Audio MIC input jack for the UDA1380 audio codec Audio LINE input jack for the UDA1380 audio codec...

  • Page 69: Table 18-2. Description Of The Buttons And Switches

    Maximum signal input values are indicated in the corresponding controller User's Manual/Data Sheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. © PHYTEC America LLC 2009...

  • Page 70: Jumpers

    L-714e_1 19 Jumpers Fig. 19-1. Jumper Locations and Default Settings The phyCORE-LPC3250 Carrier Board comes pre-configured with 51 removable jumpers (JP). The jumpers allow the user flexibility of rerouting a limited amount of signals for development constraint purposes. Table 19-1 below lists the 51 removable jumpers, their default positions, and their functions in each position.

  • Page 71: Table 19-1. Jumper Settings

    I2SRX_WS1 signal connected to audio codec. JP12 Open I2SRX_CLK1 signal disconnected from audio codec. Closed I2SRX_CLK1 signal connected to audio codec. JP13 Open Audio reset controlled by external RC circuit. Closed Audio reset controlled by processor signal GPO_02/MAT1.0/LCD0. © PHYTEC America LLC 2009...
  • Page 72 Open Processor signal GPI_2 free for external use. Closed Processor signal GPI_2 used to read User Button 2 (BTN2) status. JP29 Open phyCORE-LPC3250 on-board RS-232 transceiver operational. Closed phyCORE-LPC3250 on-board RS-232 transceiver shutdown. JP30 Open Processor debug mode enabled. Closed Processor boundary scan mode enabled.
  • Page 73 LCD_MODE1 bit set to 0. JP50 Open LCD_MODE2 bit set to 1. Closed LCD_MODE2 bit set to 0. JP51 Open Processor signal GPO_4 free for external use. Closed Processor signal GPO_4 used to control LCD_ENA input. © PHYTEC America LLC 2009...

  • Page 74: Phycore-Lpc3250 Som Connectivity

    L-714e_1 20 phyCORE-LPC3250 SOM Connectivity Fig. 20-1. phyCORE-LPC3250 SOM Connectivity to the Carrier Board Connector X1 on the Carrier Board provides the phyCORE-LPC3250 System on Module connectivity. The connector is keyed for proper insertion of the SOM. Figure 20-1 above shows the location of connector X1, along with the pin numbering scheme.

  • Page 75: Power

    21 Power Fig. 21-1. Powering Scheme The phyCORE-LPC3250 Carrier Board powering scheme provides a flexible platform for a variety of powering configurations. Board power sourcing includes a wall adapter, Power-over-Ethernet, or a battery supply. A number of the on-board power supplies have configurable input sources along with shutdown control during a sleep.
  • Page 76 3.0V deep sleep supply directly to the battery output (VCC_IN essentially). The phyCORE-LPC3250 Carrier Board allows you to test both configurations with the battery you decide to use in your end application.

  • Page 77: Wall Adapter Input

    21.1 Wall Adapter Input Permissible input voltage: +5 VDC regulated. The primary input power to the phyCORE-LPC3250 Carrier Board is located at connector X10 as shown in Figure 21-2 above. The required load current capacity of the power supply depends on the specific configuration of the phyCORE-LPC3250 mounted on the Carrier Board, in addition to the particular interfaces enabled while executing software.

  • Page 78: Power Over Ethernet (Poe)

    The IEEE PoE standard restricts the maximum amount of power a PSE must provide and therefore a PD can consume. The phyCORE-LPC3250 PoE circuit was designed to provide up to 8.5W of power to the board. Note that this is less than the wall adapter can supply and less than the board can potentially consume.

  • Page 79: Battery Charging Circuit

    1.1A charging current. You should consult PHYTEC before using your own battery. To use the battery option to power the board plug the PHYTEC supplied lithium-ion battery into connector X9 on the Carrier Board. If the board is already powered via the PoE circuit, or the wall adapter input, the...

  • Page 80: Supply (U10)

    25milliOhms. The shunt resistor should be small enough to not affect the output voltage (it will be reduced by the voltage drop across the shunt), but large enough to have a discernible measurement from general noise. © PHYTEC America LLC 2009...

  • Page 81: Jtag Connectivity

    JTAG probe to ensure compatibility. Table 22-1. LPC3250 JTAG Connector X12 Pin Descriptions Pin Signal Description VTREF Ref voltage input. Connected to VCC=3.15V. VSUPPLY Supply input. Connected to VCC=3.15V. /TRST Test controller reset input with internal 10k pull-up. Ground. © PHYTEC America LLC 2009...

  • Page 82: Table 22-2. Compatible Jtag Probes For The Phycore-Lpc3250 Carrier Board

    LPC3250. Alternatively this jumper can be set to the 2+3 position, configuration the interface to drive the /RESET_BAT input to the phyCORE-LPC3250. This jumper must be changed in conjunction with jumper JP58. Both JP41 and JP58 must be in the 1+2 position, or both in the 2+3 position.
  • Page 83 JP58. Both JP41 and JP58 must be in the 1+2 position, or both in the 2+3 position. The /RESET_SYS signal is the system reset input to the phyCORE-LPC3250. Driving this signal LOW will cause a system reset. The /RESET_BAT signal is the system + sleep reset input to the phyCORE- LPC3250.

  • Page 84: Deep Sleep Circuit

    The deep sleep circuit is responsible for power supply control and tracking deep sleep status. This circuit coupled with sleep designed features on the phyCORE-LPC3250 allow the processor to shut down primary system power supplies while maintaining SDRAM and RTC power.

  • Page 85: Fig. 23-2. Deep Sleep Circuit Block Diagram

    RTC or SDRAM supplies fail or the sleep voltage VDS_3V0 fails (moni- tored as VBAT on the SBC) this signal will go LOW causing a reset to the deep sleep state flip-flop DFF1 (set to wake state). © PHYTEC America LLC 2009...
  • Page 86 When pressed the system should begin the sleep shutdown process via software. The Power Switch output is routed to both the deep sleep control circuitry and the phyCORE-LPC3250 SOM. The deep sleep circuitry only responds to the power switch when power has been removed.

  • Page 87: Fig. 23-3. Deep Sleep State Diagram

    JP17 Connects processor output signal GPO_17 to the DS_SET input signal of the deep sleep state flip-flop DFF1, allowing the processor to set the sleep state. Remove this jumper to free GPO_17 for external use. © PHYTEC America LLC 2009...

  • Page 88: Deep Sleep Supply (U11)

    OFF input. By default this jumper is closed, shutting off the 3.15V supply when the sys- tem enter deep sleep. Remove this jumper to keep 3.15V circuitry alive during a sleep. 3.15V circuitry includes the phyCORE-LPC3250 along with most of the supporting cir- cuitry on the Carrier Board. Reference the Carrier Board schematics for details.

  • Page 89: Audio Interface

    The UDA1380 is interfaced to the phyCORE-LPC3250 via the I²S port 1 for audio data and the I²C port 1 for codec configuration. The codec is clocked off of the processors I2STX_WS1 signal with the help of internal codec PLLs.
  • Page 90 Open this jumper to free this signal for external use. JP13 Connects the LCD0/GPO_02 processor signal to the audio codec reset input. By default this jumper is closed. Open this jumper to free this signal for external use. © PHYTEC America LLC 2009...

  • Page 91: Ethernet Connectivity

    One RJ-45 connector is provided at X7. This connector provides both a connection to the Ethernet data signals and the Power-over-Ethernet power signals. A LINK and ACTIVITY LED are provided on the Carrier Board at D36 and D41. One configuration jumper is provided to disable the phyCORE-LPC3250 Ethernet clock oscillator.
  • Page 92 A detailed list of applicable configuration jumpers is presented below. JP14 Enables/disables the phyCORE-LPC3250 Ethernet oscillator. By default this jumper is open, enabling the phyCORE-LPC3250 Ethernet oscillator (required for Ethernet functionality). If the Ethernet interface is not used, or the keyboard interface is required, close this jumper to disable the on-board Ethernet clock oscillator.

  • Page 93: Usb Connectivity

    26 USB Connectivity Fig. 26-1. USB Interface Connectors and Jumpers The USB interface provides connectivity to the phyCORE-LPC3250 USB OTG functionality. Three connectors are provided for testing convenience: (1) a Standard-A Host connector X18, (2) a Standard-B Peripheral connector X16, (3) and a Mini-AB OTG connector X17. All three connectors connect to the same USB interface.
  • Page 94 4.7uF of capacitance on USB_VBUS. This configu- ration is required when operating as an OTG device. When operating as a dedicated USB host, close this jumper to add the required 120uF of capacitance on USB_VBUS required by the USB specification. © PHYTEC America LLC 2009...

  • Page 95: Lcd Connectivity

    27 LCD Connectivity Fig. 27-1. LCD Interface Connectors and Jumpers The phyCORE-LPC3250 Carrier Board provides a flexible LCD connection interface to support various PHYTEC provided LCD boards. The Universal LCD Connector X26 provides power, and buffered signals to connecting LCDs.

  • Page 96: Fig. 27-2. Lcd Blue Signal Mapping In 24-Bit Mode With A 24-Bit Lcd

    Table 28 shows a detailed mapping of the LPC3250 LCD port signals through the CPLD. In general the CPLD is acting as a buffer, mapping LCD23...16 directly to LCD_BLUE7...0, LCD15...8 to LCD_GREEN7...0, and LCD7...0 to LCD_RED7...0. The only time this is not true is for the lower LCD color © PHYTEC America LLC 2009...
  • Page 97 LCD_BLUE3...0 Driven LOW → • LCD15...12 LCD_GREEN7...4 → • LCD11...8 Free for external use → • LCD_GREEN3...0 Driven LOW → • LCD7...4 LCD_RED7...4 → • LCD3...0 Free for external use → • LCDRED3...0 Driven LOW © PHYTEC America LLC 2009...

  • Page 98: Table 27-1. Lpc3250 Lcd Port To Buffered Cpld Signal Mapping

    LCD_GREEN3 LCD10 LCD_GREEN2 LCD09 LCD_GREEN1 LCD08 LCD_GREEN0 LCD07 LCD_RED7 LCD06 LCD_RED6 LCD05 LCD_RED5 LCD04 LCD_RED4 LCD03 LCD_RED3 LCD02 LCD_RED2 LCD01 LCD_RED1 LCD00 LCD_RED0 LCDFP LCD_VSYNC LCDLP LCD_HSYNC LCDCP LCD_PCLK LCDAC LCD_DATAVALID LCDLE LCD_LINE_END LCDCLKIN LCD_CLKIN © PHYTEC America LLC 2009...

  • Page 99: Table 27-2. Lcd Mode Jumper Summary (Jp48, Jp49, Jp50)

    LCD 5.0V status indicator. When illuminated the 5.0V supply to the LCD connector X26 is active. LCD 3.3V status indicator. When illuminated the 3.3V supply to the LCD connector X26 is active. © PHYTEC America LLC 2009...

  • Page 100: Gpio Expansion Connector

    28 GPIO Expansion Connector Fig. 28-1. GPIO Expansion Connector The GPIO expansion port connector X2 provides a 1:1 mapping of most of the phyCORE-LPC3250 mating connector X1 signals. Additional signals generated on the Carrier Board are also routed to the GPIO expansion port connector X2.

  • Page 101: Connectivity

    29 RS-232 Connectivity Fig. 29-1. RS-232 Interface Connectors and Jumpers Female DB-9 connectors P1A and P1B provide connectivity to the phyCORE-LPC3250 UART2, UART3, and UART5 interfaces at RS-232 levels. Connector P1A is dedicated to UART5, while P1B is shared between UART2 and UART3. In addition to the traditional DB-9 style connectors a 0.1"/2.54mm header at X13 is provided for easy access the UART2 and UART3 signals at RS-232 levels.

  • Page 102: Table 29-1. Connector P1A (Uart5) Pin Descriptions

    UART3/UART2 header connector X13. Pin number 1 can be found by looking for a 1 on the PCB silk screen next to connector X13. Table 29-3 provides a detailed description of the signals at header connector X13. © PHYTEC America LLC 2009...

  • Page 103: Table 29-3. Uart3/Uart2 Header Connector X13 Pin Descriptions

    RS-232 interface, or free up signals for alternative use. A detailed list of applicable configuration jumpers is presented below. JP29 Shuts down the RS-232 transceiver on the phyCORE-LPC3250. By default this jumper is in the OPEN position. Close this jumper to reduce system power if the RS-232 interface is not needed.

  • Page 104: Table 29-4. Configuring Db-9 Connector P1B For Uart3 Or Uart2 Operation

    UART2 transmit signal UART3_DTR_RS232 routed to the transmit pin of the DB-9 connector P1B. UART2 Operation JP54 = 2 + 3 UART2 receive signal UART3_DSR_RS232 routed to the receive pin of the DB-9 connector P1B. © PHYTEC America LLC 2009...
  • Page 105 Note that the UART3 and UART2 CTS and RTS signals are multiplexed on the same pins and do not need to be rerouted as do the transmit and receive signals. That is, UART3 RTS is also UART2 HRTS, and UART3 CTS is also UART2 HCTS. © PHYTEC America LLC 2009...

  • Page 106: Sd/Mmc Connectivity

    L-714e_1 30 SD/MMC Connectivity Fig. 30-1. SD/MMC Interface Connectors and Jumpers Connector X15 provides connectivity to the phyCORE-LPC3250's SD/MMC card interface. In addition header connector X24 has been provided for easy access to the SD/MMC card signals for probing purposes.
  • Page 107 SD/MMC card write protect state. Set this jumper to the 2+3 position when using the SD/MMC card slot with SDIO devices. Remove this jumper to free up GPIO_0 for external use. © PHYTEC America LLC 2009...

  • Page 108: Sdio Connectivity

    31 SDIO Connectivity Fig. 31-1. SDIO Interface Connectors and Jumpers Connector X14 provides connectivity to the phyCORE-LPC3250's SDIO controller interface. In addition header connector X23 has been provided for easy access to the SDIO card signals for probing purposes. © PHYTEC America LLC 2009...

  • Page 109: Table 31-1. Sdio Easy Access Header Connector X23 Signal Descriptions

    SDIO interface. Note that the current measurement at this location is the sum of the current drawn by the SDIO controller on the phyCORE- LPC3250, and the device attached to the SDIO connector X14. SD/MMC style card connector. © PHYTEC America LLC 2009...
  • Page 110 Part II, Chapter 31: SDIO Connectivity L-714e_1 16-pin easy access signal header. © PHYTEC America LLC 2009...

  • Page 111: Keyboard Connectivity

    Fig. 32-1. Keyboard Interface Connector and Dip Switches The phyCORE-LPC3250 Carrier Board provides an easy access 0.1"/2.54mm header connector at X11 to the keyboard port pins. In addition two sets of dip switches are provided to add the necessary 1M pull-up, and 22k pull-down resistors as illustrated in the LPC3250 User's Manual.

  • Page 112: Table 32-1. Dip Switch S5 Positions And Associated Signals

    Ethernet receive error input/Keyboard COL2 input ENET_TX_EN Ethernet transmit enable output/Keyboard ROW3 output ENET_CRS Ethernet carrier sense input/Keyboard COL3 input ENET_TXD0 Ethernet transmit data 0 output/Keyboard ROW4 output ENET_RXD0 Ethernet receive data 0 input/Keyboard COL4 input © PHYTEC America LLC 2009...
  • Page 113 Ethernet receive data valid/Keyboard COL6 input ENET_MDIO I/O Ethernet MI data input/output/Keyboard ROW7 output ENET_COL Ethernet collision detect input/Keyboard COL7 input ENET_RXD3 Ethernet receive data 3 input ENET_RXD2 Ethernet receive data 2 input Ground Ground © PHYTEC America LLC 2009...

  • Page 114: User Buttons

    User button 1 (labeled as BTN1). Pressing this button generates a debounced, active HIGH going pulse to processor signal GPI_3 for the duration of the press. Holding this button will keep the output to GPI_3 held HIGH. Releasing this button will keep the output to GPI_3 held LOW. © PHYTEC America LLC 2009...
  • Page 115 BTN1 to GPI_3. Open this jumper if GPI_3 is needed for external use. JP28 Connects the output of BTN2 (S4) to processor signal GPI_2. By default this jumper is closed, connecting BTN2 to GPI_2. Open this jumper if GPI_2 is needed for external use. © PHYTEC America LLC 2009...

  • Page 116: User Leds

    Red User LED 1 (labeled as LED1). Drive processor signal GPO_1 HIGH to turn this LED on and LOW to turn this LED off. Red User LED 2 (labeled as LED2). Drive processor signal GPO_14 HIGH to turn this LED on and LOW to turn this LED off. © PHYTEC America LLC 2009...
  • Page 117 Connects the processor signal GPO_14 to the User LED 2 input. By default this jumper is closed, allowing the processor to control LED 2 via GPO_14. Open this jumper to prevent LED 2 from toggling if GPO_14 needs to be used externally. © PHYTEC America LLC 2009...

  • Page 118: User Adc Potentiometer

    Connects the processor's analog-to-digital converter ADIN2 channel to the output of the User ADC potentiometer R175. By default this jumper is closed, connecting the pot to the ADIN2 input. Open this jumper if the ADIN2 input is needed for external use. © PHYTEC America LLC 2009...

  • Page 119: Boot Mode Selection

    Fig. 36-1. Boot Mode Selection Jumper The boot mode jumper JP21 is provided to configure the boot mode after a reset. By default the boot mode jumper is closed, configuring the phyCORE-LPC3250 for UART5 boot. Alternatively JP21 can be removed, resulting the normal boot mode.

  • Page 120: System Reset Button

    S1 is pressed, but the deep sleep circuitry is also reset. If you wish to have a configuration where pressing S1 issues a system reset, but does not reset the sleep circuitry, see section 3 to configure the reset input jumper on the phyCORE-LPC3250 to drive /RESET_SYS instead of the default /RESET_BAT signal.

  • Page 121: Watchdog Circuit

    38 Watchdog Circuit Fig. 38-1. Watchdog Enable Jumper For mission critical applications the phyCORE-LPC3250 SOM provides a processor independent watchdog circuit to reset the processor should the system hang. To enable the on-board watchdog circuit jumper JP38 must be closed. By default JP38 is open, disabling the watchdog circuit. JP38 controls the connection and disconnection of the processor signal GPO_20.

  • Page 122: Part Iii: Pcm-988/Gpio Expansion Board

    Part 3 of this 3 part manual provides detailed information on the GPIO Expansion Board and how it enables easy access to most phyCORE-LPC3250 SOM signals. The information in the following chapters is applicable to the 1190.2 PCB revision of the GPIO Expansion Board.

  • Page 123: Introduction

    The Expansion Board interfaces the SOM and Carrier Board via the Carrier Board expansion bus connector X2. Nearly all signals from the phyCORE-LPC3250 extend in a strict 1:1 assignment to the Expansion Bus connector. These signals, in turn, are routed in a similar manner to the patch field on the Expansion Board.

  • Page 124: Table 39-1. Signals Removed From The Gpio Expansion Connector

    The following chapters and tables, arranged in functional groups, show the relationship between the phyCORE-LPC3250 signal, the location on the GPIO Expansion Bus connector, and where to find the associated signal on the Expansion Board patch field. Please note that because there are a number of multiplexed pins on the LPC3250 processor, a particular pin may fall in multiple groups, and hence will be repeated in several tables.

  • Page 125: System Signal Mapping

    Table 40-1 provides signal mapping for the SOM system signals. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).

  • Page 126: Memory Bus Signal Mapping

    SOM memory bus signals for connection of external memory mapped devices. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).
  • Page 127 © PHYTEC America LLC 2009...

  • Page 128: Lcd Signal Mapping

    Table 42-1 provides signal mapping for the SOM LCD signals. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).

  • Page 129: Uart Signal Mapping

    TTL levels. All signals that end in RS232 are at RS-232 levels. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).

  • Page 130: 44 I²C Signal Mapping

    Table 44-1 provides signal mapping for the SOM I²C signals. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).

  • Page 131: Gpio Signal Mapping

    SOM GPI, GPO, and GPIO signals. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).

  • Page 132: Usb Signal Mapping

    Table 46-1 provides signal mapping for the SOM USB signals. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).

  • Page 133: Ssp Signal Mapping

    Table 47-1 provides signal mapping for the SOM SSP signals. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).

  • Page 134: 48 I²S Signal Mapping

    Table 48-1 provides signal mapping for the SOM I²S signals. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).

  • Page 135: Power Signal Mapping

    SOM power signals. These signals include all VCC and ground pins. The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-LPC3250 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see Chapter 2).

  • Page 136: Revision History

    Revision History L-714e_1 Revision History Table 50-1. Revision History Date Version Number Changes in this Manual 09/02/2008 L-714e_0 Preliminary release. 01/21/2009 L-714e_1 First official release. © PHYTEC America LLC 2009...

  • Page 137: Index

    30 JP17 78 description 30 JP18 79 dimensions, SOM 52 JP19 79 JP2 70 EEPROM JP20 79 configuration data 40 JP21 110 densities 39 JP22 79 U19 40 JP23 108 Ethernet JP24 79 © PHYTEC America LLC 2009...
  • Page 138 VCC_1V2 & VCC_1V8 settings 26 /RESET_BAT 33 VCC_CORE configuration 27 /RESET_SYS 33 VCC_RTC & VCC_SDRAM settings 27 JTAG /SRST 73 system reset button 111 keyboard thresholds 28 connectivity 102 revision history 127 disabling ethernet interface 102 RS-232 © PHYTEC America LLC 2009...
  • Page 139 SPI EEPROM, see EEPROM Stage 1 Loader, see boot system memory, see memory System on Module 1 technical specifications 52 temperature operating 52 storage 52 applicable connectors 46 connectivity 84 external power supply 45 I2C address 45 © PHYTEC America LLC 2009...

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