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Phytec phyCORE-MPC5554 Hardware Manual

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phyCORE-MPC5554
Hardware Manual
Edition January 2007
A product of a PHYTEC Technology Holding company

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Summary of Contents for Phytec phyCORE-MPC5554

  • Page 1 Hardware Manual Edition January 2007 A product of a PHYTEC Technology Holding company...
  • Page 2 PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.
  • Page 3 Preface......................1 Introduction..................3 1.1 Block Diagram ................6 1.2 View of the phyCORE-MPC5554..........7 1.3 Minimum Requirements to Operate the phyCORE-MPC5554 ... 9 Pin Description .................. 11 Jumpers....................25 Power Requirements................. 35 4.1 Voltage Supervision and Reset ..........36 System Start-Up Configuration ............
  • Page 4 11.5 Release Notes................86 Technical Specifications ..............87 Hints for Handling the Module ............91 Design Considerations - Check List ..........92 Revision History................93 Appendices..................94 A.1 Release Notes................94 Index ......................95 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 5 Block Diagram phyCORE-MPC5554........6 Figure 2: Top View of the phyCORE-MPC5554 Revision 1239.1... 7 Figure 3: Bottom View of the phyCORE-MPC5554 Revision 1239.1 ..8 Figure 4: Pinout of the phyCORE-MPC5554 (Bottom View) ....11 Figure 5: Numbering of the Jumper Pads..........25...
  • Page 6 Signal Pin Assignment for the phyCORE-MPC5554 / Development Board / Expansion Board ........80 Table 16: Pin Assignment Power Supply for the phyCORE-MPC5554 / Development Board / Expansion Board ........81 Table 17: Pin Assignment of the Reduced JTAG/OnCE/Nexus Pin Header X2 ................
  • Page 7 Contents © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 9 (such as electricians, technicians and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product’s pin header rows are longer than 3 m. © PHYTEC Messtechnik GmbH 2006...
  • Page 10 The phyCORE-MPC5554 is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports...
  • Page 11 The phyCORE-MPC5554 is a subminiature (84 x 57 mm) insert-ready Single Board Computer populated with Freescale's PowerPC MPC5554 microcontroller. Its universal design enables its insertion in a wide range of embedded applications.
  • Page 12 The phyCORE-MPC5554 offers the following features: • Single Board Computer in subminiature form factor (84 x 57 mm) according to phyCORE specifications •...
  • Page 13 JTAG emulation • I C Real-Time Clock with calendar and alarm function • JTAG/OnCE/Nexus test/debug port • industrial temperature range (-40…+85°C) Please contact PHYTEC for more information about additional product configurations. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 14 ETPUA[31..0], TCRCLKA eTPU B ETPUB[31..0], TCRCLKB 40 channels, 12-bit eQADC 0 / 1 AN[39..0] ETRIG[1,2], VRH 12-Bit 12-Bit DAC, 1 channel 1 channel C Bus JTAG/Nexus JTAG/Nexus Debug Port Figure 1: Block Diagram phyCORE-MPC5554 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 15 Introduction 1.2 View of the phyCORE-MPC5554 Figure 2: Top View of the phyCORE-MPC5554 Revision 1239.1 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 16 Figure 3: Bottom View of the phyCORE-MPC5554 Revision 1239.1 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 17 We recommend connecting all available +3V3 and +5 V input pins to the power supply system on a custom carrier board housing the phyCORE-MPC5554 and at least the matching number of DGND pins neighboring the +3V3 and +5 V pins.
  • Page 18 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 19 As Figure 4 indicates, all controller signals extend to surface mount technology (SMT) connectors (0.635 mm) lining two sides of the module (referred to as phyCORE-connector; refer to section 12). This allows the phyCORE-MPC5554 to be plugged into any target application like a "big chip". Figure 4:...
  • Page 20 FPGA_B4_IO5 FPGA_B4_IO6 Functionality depends on the loaded FPGA FPGA_B4_IO7 firmware. FPGA_B4_IO12 FPGA_B4_IO13 The signals of a blank device are inputs with an FPGA_B4_IO14 internal weak pull-up. FPGA_B4_IO15 FPGA_B4_IO20 FPGA_VDDIO4 (Jumper J10) FPGA_B4_IO21 FPGA_B4_IO22 FPGA_B4_IO23 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 21 I/O eTPU B channel 10 Alternative: ETPUB26, GPIO157 ETPUB8 I/O eTPU B channel 8 Alternative: ETPUB24, GPIO155 ETPUB6 I/O eTPU B channel 6 Alternative: ETPUB22, GPIO153 ETPUB4 I/O eTPU B channel 4 Alternative: ETPUB20, GPIO151 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 22 Alternative: GPIO211 IRQ3 IRQ3 interrupt request of the MPC5554 Alternative: GPIO212 4B, 9B, 14B, DGND Ground 0 V 19B, 24B, 29B, 34B, 39B, 44B, 49B, 54B, 59B, 64B, 69B, 74B, 79B, 84B, 89B, 94B, 99B © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 23 The signals of a blank device are inputs with an FPGA_B3_IO9 internal weak pull-up. FPGA_B3_IO10 FPGA_B3_IO11 ETPUB31 I/O eTPU B channel 31 Alternative: GPIO178 ETPUB29 I/O eTPU B channel 29 Alternative: GPIO176 ETPUB27 I/O eTPU B channel 27 Alternative: GPIO174 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 24 I/O eTPU A channel 15 Alternative: PCSB5, GPIO129 ETPUA13 I/O eTPU A channel 13 Alternative: PCSB3, GPIO127 ETPUA11 I/O eTPU A channel 11 Alternative: ETPUA23, GPIO125 ETPUA9 I/O eTPU A channel 9 Alternative: ETPUA21, GPIO123 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 25 When the alternative function is used, the solder jumper J22 must be open in order to disconnect the receive output of the RS-232 transceiver. TXDB Transmit line of the MPC5554 eSCI channel B. Alternative: PCSD1, GPIO91 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 26 DSPI A chip select 1 of the MPC5554. Alternative: PCSB2, GPIO97 PCSA3 DSPI A chip select 3 of the MPC5554. Alternative: SIND, GPIO99 PCSA5 DSPI A chip select 5 of the MPC5554. Alternative: PCSB3, GPIO101 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 27 AN18 AN16 77C, 82C, 87C, AGND Analog Ground 0 V 92C, 97C AN14 eQADC analog input 14 of the MPC5554. Alternative: MA2, SDI AN12 eQADC analog input 12 of the MPC5554. Alternative: MA0, /SDS © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 28 If the alternative function is used, the solder jumper J21 must be opened in order to disconnect the receive output of the RS-232 transceiver. TXDA Transmit line of the MPC5554 eSCI UART A. Alternative: GPIO89 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 29 I/O GPIO205 of the MPC5554 GPIO207 I/O GPIO207 of the MPC5554. Alternative: ETRIG1 SCKA I/O DSPI A clock of the MPC5554. Alternative: PCSC1, GPIO93 PCSA0 DSPI A chip select 0 of the MPC5554. Alternative: PCSD2, GPIO96 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 30 AN21 AN19 AN17 AN15 eQADC analog input 15 of the MPC5554. Alternative: FCK AN13 eQADC analog input 13 of the MPC5554. Alternative: MA1, SDO AN11 eQADC analog input 11 of the MPC5554. Alternative: ANZ © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 31 Alternative: DAN2- eQADC analog input 3 of the MPC5554. Alternative: DAN1- eQADC analog input 1 of the MPC5554. Alternative: DAN0- 100D Reference voltage of the eQADC module. Table 1: Pinout of the phyCORE-Connector X2 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 32 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 33 Jumpers 3 Jumpers For configuration purposes, the phyCORE-MPC5554 has 37 solder jumpers, some of which have been installed prior to delivery. Figure 5 illustrates the numbering of the jumper pads, while Figure 6 and Figure 7 indicate the location of the jumpers on the board.
  • Page 34 Figure 6: Location of the Jumpers (Controller Side) and Default Settings (phyCORE-MPC5554 Standard Version) © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 35 Jumpers Figure 7: Location of the Jumpers (Connector Side) and Default Settings (phyCORE-MPC5554 Standard Version) Jumper J19 may have different settings according to the purchased memory configuration of the phyCORE-MPC5554. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 36 1 + 2 The serial memory is supplied with VDD3V3. 2 + 3 The serial memory is supplied with VPD. Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 37 0R in SMD 0805 J14 selects the input voltage for the MPC5554 VDDEH1 power input. 1 + 2 VDDEH1 is connected to VDD3V3. 2 + 3 VDDEH1 is connected to VDD5V. Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 38 4 + 5, 7 + 8 BA0=A9, BA1=A8: 32 MBit memory devices at U5-8. 4 + 7, 8 + 9 BA0=A8, BA1=DGND: 64 MBit memory devices at U5-6 only. Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 39 Please refer to the corresponding memory data sheet for more detailed information. open closed Package Type 0R in SMD 0402 J24-27 J24-27 are for internal PHYTEC use only. Do not modify the configuration! open closed Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2006...
  • Page 40 J32 connects the MPC5554 signals GPIO203 and GPIO204 to the FPGA signals /FPGA_SLEEP and /FPGA_PROG. 1 + 2 Connects MPC5554 GPIO203 to /FPGA_SLEEP. 3 + 4 Connects MPC5554 GPIO204 to /FPGA_PROG. Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 41 Please refer to the corresponding memory data sheet for more detailed information. 1 + 2 Connects pin 6 to VDD3V3. 2 + 3 Connects pin 6 to DGND. Package Type 0R in SMD 0402 Table 2: Jumper Settings © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 42 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 43 Power Requirements 4 Power Requirements The phyCORE-MPC5554 must be supplied with two different supply voltages: +3.3 V ± 5 % with 1A ** Supply voltage VDD3V3 Pins at Connector X2 1C, 2C, 1D, 2D, 4D, 5D +5 V ± 10 % with 100mA **...
  • Page 44 /RESET is a bi-directional (open-collector) signal that can be connected to more then one source. For instance, /RESET is also connected to the JTAG/OnCE connector of the phyCORE module. /RESET has a 10kOhm pull-up resistor. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 45 System Start-Up Configuration System Start-Up Configuration The phyCORE-MPC5554 supports four different software start-up modes: • Internal Flash Memory • External Memory controlled by /CS0 • SCI UART • FlexCAN Internal/External Memory Boot The decision which mode is used after /RESET goes from active to inactive state is defined by the external signal /RSTCFG (X2C9).
  • Page 46 Refer to the MPC5554 reference manual for a detailed description of the boot modes,. Clock Configuration The default clock configuration is set to "Crystal reference". For this setting jumper J1 and J2 are pre-configured at the time of assembly. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 47 Communication with the small non-volatile memory device (EPROM, FRAM or SRAM) is established over the I C bus. This memory device can be used for storage of system parameters or configuration data. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 48 6.1 External Standard Flash Memory (U3, U4) The Flash memory devices used on the phyCORE-MPC5554 operate in 16-bit mode and are organized in 32-bit data bus with. The device at U3 connects to the low data bus while device U4 connects to the high data bus.
  • Page 49 The memory is generally accessed via /CS1 without wait states. The phyCORE-MPC5554 can be populated with memory devices of various capacities. Generally, each memory bank can only be populated with memory devices of a consistent size. Solder jumper J19 is used to configure the memory capacity and pre-installed at time of delivery.
  • Page 50 6.3 Serial Memory (U15) The phyCORE-MPC5554 features a non-volatile memory device with a serial I C interface. This memory can be used for storage of configuration data or operating parameters, that must not be lost in the event of a power interruption. Depending on the module's configuration, this memory can be in the form of an EEPROM, FRAM or SRAM.
  • Page 51 Table 7: Serial Memory I C Address (Examples) Address lines A1 and A2 are not always made available by certain serial memory types. This should be noted when configuring the I bus slave address. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 52 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 53 7 FPGA System Logic Device U21 The FPGA logic device U21, supplied by Lattice Semiconductor, is responsible for routing resources on the phyCORE-MPC5554 and provides a very flexibly way to connect and operate application- specific hardware components or interfaces in a target design. In...
  • Page 54 Molex connector X2 and can be used for application-specific features. The following FPGA signals are available through the phyCORE- connector X2: FPGA_B1_IO[25..0] 26 signals FPGA_B4_IO[25..0] 26 signals FPGA_B2_IO[19..0] 20 signals FPGA_B3_IO[11..0] 12 signals ========================== Number of user I/O 84 signals © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 55 7.1 FPGA Firmware Development A basic firmware project with pin and signal assignment is provided by PHYTEC. This project is written in VHLD and can easily be extended with customer-specific functionality. The required development tool is called ispLever and is provided by Lattice Semiconductor.
  • Page 56 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 57 RS-232 transceiver located phyCORE-MPC5554 at U10. This device adjusts the signal levels of the TXDA/RXDA and TXDB/RXDB lines (MPC5554 eSCI UART). The RS-232 interface enables connection of the module to a COM port on a host-PC or other peripheral devices. In this instance, the...
  • Page 58 CAN signals is required. For larger CAN bus systems, an external de-coupler device should be implemented to optically isolate the CAN transceiver and the phyCORE-MPC5554. To add external circuits for optical isolation, the CAN transceivers must be removed and the CAN bus signals bypassed by means of solder jumpers J30 and J31.
  • Page 59 The footprint of X3 is designed for a 14-pin header with 2.0 mm pin spacing. The pin assignment is shown in Figure 9. Pin header X3 is not installed on the standard phyCORE-MPC5554 module. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 60 (X2) In order to connect a true Nexus port, an external 38-pin connector must be located on the customer application board. The PHYTEC phyCORE-MPC5554 Development Board (part number PCM-979) features such Nexus connector at X2 and can be used as an example.
  • Page 61 Ethernet Controller LAN91C111 Ethernet Controller Connection of the phyCORE-MPC5554 to the world wide web or a local network is possible if the optional LAN91C111 10/100 Mbit/s Ethernet controller populates the module at U20. This section only describes the functional characteristics of the LAN91C111 as implemented on the phyCORE-MPC5554.
  • Page 62 IP number to the hardware's MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE-MPC5554 is located on the bar code sticker attached to the module.
  • Page 63 24-hour format Automatic word address incrementing Programmable alarm, timer and interrupt functions If the phyCORE-MPC5554 is equipped with a battery (VBAT), the Real-Time Clock runs independently of the board’s power supply. The Real-Time Clock is programmed via the I C bus (address 0xA2 / 0xA3).
  • Page 64 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 65 Development Board PCM-979 phyCORE Development Board PCM-979 PHYTEC Development Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start-up and subsequent communication to and programming of applicable PHYTEC Single Board Computer (SBC) modules. Development...
  • Page 66 IRQ push button Reset push button green power LED, monitors +5 V VDD-CAN green power LED, monitors +5 V VDD5V green power LED, monitors +3V3 VDD3V3 red user LED, controlled by MPC5554 I/O line EMIOS0 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 67 Sheets. As damage from improper connections varies according to use and application, it is the user‘s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 68 Figure 10: Location of Connectors, Buttons and LED's on the phyCORE Development Board PCM-979 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 69 Jumpers on the phyCORE Development Board PCM-979 Peripheral components of the phyCORE Development Board PCM-979 can be connected to the signals of the phyCORE-MPC5554 by setting the applicable jumpers. The Development Board's peripheral components are configured for use with the phyCORE-MPC5554 by means of removable jumpers. If no jumpers are set, no signals are connected to the DB-9 connectors, the control and display units or the CAN transceivers.
  • Page 70 Figure 12: Location of the Jumpers (View of the Component Side) © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 71 Figure 13 shows the factory default jumper settings for operation of the phyCORE Development Board PCM-979 with the standard phyCORE-MPC5554. Jumper settings other functional configurations of the phyCORE-MPC5554 module mounted on the Development Board are described in section 11.3. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 72 Figure 13: Default Jumper Settings of the phyCORE Development Board PCM-979 with phyCORE-MPC5554 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 73 Development Board PCM-979 supported by the phyCORE-MPC5554 and appropriate jumper settings to activate these components. Depending on the specific configuration of the phyCORE-MPC5554 module, alternative jumper settings can be used. These jumper settings are different from the factory default settings as shown in Figure 13 and enable alternative or additional functions on the phyCORE Development Board PCM-979 depending on user needs.
  • Page 74 3.5 mm ≥ 1500 mA Figure 14: Connecting the Supply Voltage at X5 Caution: Do not remove any of these jumpers and power the board. One missing main supply voltage can destroy the module! © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 75 Second Serial Interface at Socket P2B Socket P2B is the top socket of the double DB-9 connector at P2. Pin 2 TXDB Pin 3 RXDB Pin 5 GND Figure 16: Pin Assignment of P2B as Second RS-232 (Front View) © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 76 Plug P1A is the bottom plug of the double DB-9 connector at P1. P1A is connected to the first FlexCAN interface (FlexCAN A) of the phyCORE-MPC5554 via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following two configurations are possible: 1.
  • Page 77 Figure 18: Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on Development Board with Galvanic Separation) Please make sure the CAN transceiver on the phyCORE-MPC5554 is not populated and Jumper J30 is closed at 1+2 and 3+4. © PHYTEC Messtechnik GmbH 2006...
  • Page 78 Plug P1B is the upper plug of the double DB-9 connector at P1. P1B is connected to the second FlexCAN interface (FlexCAN B) of the phyCORE-MPC5554 via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible: 1.
  • Page 79 Figure 20: Pin Assignment of the DB-9 Plug P1B (CAN Transceiver on Development Board) Please make sure the CAN transceiver on the phyCORE-MPC5554 is not populated and Jumper J31 is closed at 1+2 and 3+4. © PHYTEC Messtechnik GmbH 2006...
  • Page 80 The phyCORE Development Board PCM-979 offers a programmable LED at D6 for user implementations. This LED can be connected to port pin EMIOS0 of the phyCORE-MPC5554 which is available with JP7 = closed. A low-level at port pin EMIOS0 causes the LED to illuminate, LED D6 remains off when writing a high-level to EMIOS0.
  • Page 81 Figure 21: Pin Assignment Scheme of the Expansion Bus Figure 22: Pin Assignment Scheme of the Patch Field © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 82 The pin assignment on the phyCORE-MPC5554, in conjunction with the expansion bus (X7) on the Development Board and the patch field on an expansion board, is as follows: phyCORE-MPC5554 Development Board Expansion Board Expansion Bus Patch Field EXTCLK EXTCLK...
  • Page 83 BUS8 X10-2 FPGA_B1_IO3 FPGA_B1_IO3 BUS9 X11-2 FPGA_B1_IO4 FPGA_B1_IO4 BUS10 X12-2 FPGA_B1_IO5 FPGA_B1_IO5 BUS11 X13-2 FPGA_B1_IO10 FPGA_B1_IO10 BUS16 X10-4 FPGA_B1_IO11 FPGA_B1_IO11 BUS17 X11-4 FPGA_B1_IO12 FPGA_B1_IO12 BUS18 X12-4 FPGA_B1_IO13 FPGA_B1_IO13 BUS19 X13-4 FPGA_B1_IO18 FPGA_B1_IO18 BUS24 X10-5 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 84 BUS105 X11-17 ETPUB19 ETPUB19 BUS106 X12-17 ETPUB17 ETPUB17 BUS107 X13-17 ETPUB15 ETPUB15 BUS112 X10-19 ETPUB13 ETPUB13 BUS113 X11-19 ETPUB11 ETPUB11 BUS114 X12-19 ETPUB9 ETPUB9 BUS115 X13-19 ETPUB7 ETPUB7 BUS120 X10-20 ETPUB5 ETPUB5 BUS121 X11-20 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 85 GPIO31 X2-9 LAN_LEDA LAN_LEDA GPIO34 X5-9 LAN_LEDB LAN_LEDB GPIO36 X7-9 LAN_TPI- LAN_TPI- GPIO37 X8-9 LAN_TPO- LAN_TPO- GPIO39 X2-10 EMIOS17 EMIOS17 GPIO42 X5-10 EMIOS19 EMIOS19 GPIO44 X7-10 EMIOS21 EMIOS21 GPIO45 X8-10 EMIOS23 EMIOS23 GPIO47 X2-11 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 86 AN18 AN18 GPIO124 X7-22 AN16 AN16 GPIO125 X8-22 AN14 AN14 GPIO127 X2-24 AN12 AN12 GPIO130 X5-24 AN10 AN10 GPIO132 X7-24 GPIO133 X8-24 GPIO135 X2-25 GPIO138 X5-25 GPIO140 X7-25 100C 100C GPIO141 X8-25 *VPD X6-2 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 87 GPIO73 X4-15 FPGA_TCK FPGA_TCK GPIO75 X6-15 MPC_TDO MPC_TDO GPIO78 X9-15 /EVTO /EVTO GPIO80 X3-16 /EVTI /EVTI GPIO81 X4-16 /RDY /RDY GPIO83 X6-16 MCKO MCKO GPIO86 X9-16 MDO1 MDO1 GPIO88 X3-17 MDO3 MDO3 GPIO89 X4-17 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 88 GPIO128 X3-24 AN11 AN11 GPIO129 X4-24 GPIO131 X6-24 GPIO134 X9-24 GPIO136 X3-25 GPIO137 X4-25 GPIO139 X6-25 100D 100D GPIO142 X9-25 Table 15: Signal Pin Assignment for the phyCORE-MPC5554 / Development Board / Expansion Board © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 89 AGND 77C, 82C, 87C, 92C, 87C, 92C, 97C, 74D, 97C, 74D, 79D, 84D, 79D, 84D, 89D, 94D, 89D, 94D, Table 16: Pin Assignment Power Supply for the phyCORE-MPC5554 / Development Board / Expansion Board © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 90 (e.g. P&E Wiggler). Signal Pin Number Pin Number Signal MPC_TDI DGND MPC_TDO DGND MPC_TCK DGND /RESET MPC_TMS VDD3V3 DGND /RDY JCOMP Table 17: Pin Assignment of the Reduced JTAG/OnCE/Nexus Pin Header X2 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 91 /EVTI MPC_TDO VDD3V3 MDO10 /RDY MPC_TCK MDO7 MPC_TMS MDO6 MPC_TDI MDO5 JCOMP MDO4 MDO11 MDO3 vendor MDO2 MDO1 MDO0 /EVTO MCKO /MSEO1 /MSEO0 Table 18: Pin Assignment of the Full JTAG/OnCE/Nexus Pin Header X3 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 92 11.4 Technical Specification of the Development Board Figure 23 Physical Dimensions of the Development Board PCM-979 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 93 132 MHz core clock 8 MByte Voltage +5 V BurstRAM Typ. 1000 mA 8 MByte Flash LAN91C111 FPGA XP6 without any installed I/O line or expansion board Table 19: Technical Data of the Development Board PCM-979 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 94 • L6 RJ45 connector has wrong PCB footprint. Some mechanical changes were done prior population of the LAN connector. Revision: PCB# 1241.1 • Ethernet LAN is not working properly while the Expansion Board PCM977 is connected to the Expansion Bus. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 95 Technical Specification 12 Technical Specifications The physical dimensions of the phyCORE-MPC5554 are represented in Figure 24. Figure 24: Physical Dimensions (Top View) The holes with diameter 0.7 m and 0.9 mm are the positioning holes for the Molex connectors. The module edge mounting holes are plated and connected to DGND.
  • Page 96 8 MByte stand. Flash Typ. 900 mA Voltage 5 V Ethernet Typ. 60 mA FPGA XP6 Table 20: Technical Data These specifications describe the standard configuration of the phyCORE-MPC5554 as of the printing of this manual. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 97 Two different heights are offered for the receptacle sockets that correspond to the connectors populating the underside of the phyCORE-MPC5554. The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board. In order to get the exact spacing, the maximum component height (3 mm) on the underside of the phyCORE must be subtracted.
  • Page 98 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 99 Alternatively, a hot air gun can be used to heat and loosen the bonds. Integrating the phyCORE-MPC5554 in Application Circuitry Successful integration in user target circuitry depends on whether the layout for the GND connections matches those of the phyCORE module.
  • Page 100 Data line D31 represents the LSB and D0 the MSB. Address line A31 represents the LSB and A8 the MSB. Byte ordering is big Endian. Due to the conversion of little to big Endian byte ordering, the byte portions of LAN91C111 data bus are swapped to the MPC5554 data bus.
  • Page 101 AGND pins inserted for D. Module block diagram Figure 1: 12MHz changed to 8MHz Figure 10, Figure 12 and Figure 13: Description of Dual RS232 and Dual FlexCAN corrected. P2 is Dual RS232 and P1 is Dual FlexCAN. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 102 Data lines to the LAN91C1111 are now swapped due to little to big Endian conversion. Network payload data are transferred in the right order and can be copied direct to the memory. Configuration and status registers must be handled by swapping the data bytes. © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 103 Boot Modes, Serial Features BOOTCFG First CAN Interface Burst SRAM First Serial Interface Flash FPGA 5, 45 FPGA Firmware Optical Isolation FPGA System Logic Device U21 Terminating Resistor CAN Bus CAN Connector FRAM, serial CAN Interface © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 104 Plug P1B JTAG/OnCE Connector Power Requirements JTAG/OnCE/Nexus Debug Power Supply Interface 51, 82 Programmable LED Jumper Configuration, PCM-979 Jumper Location RCHW Jumper Settings Real-Time Clock Reduced JTAG/OnCE/NEXUS Connector X2 Reset LAN91C111 5, 53 Reset Button © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 105 SRAM 5, 41 SRAM, Capacity SRAM, serial Standard Flash Memory 58, 82 External 51, 58, 82, 83 Start-up System Configuration 37 Supply Voltage 9, 35 Serial Memory Synchronous Burst SRAM 58, 72 System Memory © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 106 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 107 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG Postfach 100403 D-55135 Mainz, Germany Fax : +49 (6131) 9221-33 © PHYTEC Messtechnik GmbH 2006 L-484e_1...
  • Page 108 Published by © PHYTEC Messtechnik GmbH 2006 Ordering No. L-484e_1 Printed in Germany...