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Phytec phyCORE-LPC3180 Hardware Manual

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phyCORE-LPC3180
H
M
ARDWARE
ANUAL
E
A
2007
DITION
PRIL
A product of a PHYTEC Technology Holding company

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Summary of Contents for Phytec phyCORE-LPC3180

  • Page 1 ARDWARE ANUAL 2007 DITION PRIL A product of a PHYTEC Technology Holding company...
  • Page 2 PHYTEC America LLC neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC America LLC reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.

  • Page 3: Table Of Contents

    Contents Preface ......................1 Introduction..................... 2 1.1 Block Diagram .................. 4 1.2 View of the phyCORE-LPC3180 ............5 Pin Description ..................7 Jumpers....................17 3.1 J503 MCKO Signal ................ 23 3.2 J504 A/D Positive Supply/Reference Voltage ....... 23 3.3 A/D Negative Supply/Reference Voltage........23 Power Requirements................
  • Page 4 The phyCORE-LPC3180 on the phyCORE-LPC3180 Carrier Board 45 13.1 phyCORE-LPC3180 Carrier Board Peripherals ......45 13.1.1 Jumpers on the phyCORE-LPC3180 Carrier Board... 48 13.2 Functional Components on the phyCORE-LPC3180 Carrier Board .................. 53 13.2.1 Power Supply at X304 ............53 13.2.2 System Reset Button S300 ..........
  • Page 5 Index of Figures Figure 1: Block Diagram phyCORE-LPC3180..........4 Figure 2: Top View of the phyCORE-LPC3180 (controller side) ....5 Figure 3: Bottom View of the phyCORE-LPC3180 (connector side)..... 6 Figure 4: Pinout of the phyCORE-Connector (Top View, with Cross Section Insert) ................
  • Page 6 Figure 24: Pin Assignment Scheme of the Patch Field on the Optional GPIO Expansion Board ..............62 Figure 25: phyCORE-LPC3180 Component Placement, Top View ....72 Figure 26: phyCORE-LPC3180 Component Placement, Bottom View ..73 © PHYTEC America LLC 2007...
  • Page 7 Table 19: Carrier Board LEDs ..............46 Table 20: Carrier Board Potentiometers............46 Table 21: phyCORE-LPC3180 Carrier Board Jumper Settings ....48 Table 22: P300A BOOT/RESET Signal Operating Limits ......54 Table 23: A/D Potentiometer Output Routing Options ......... 57 Table 24: Keyboard Connector X203 Signal Assignment ......
  • Page 8 Carrier Board / Expansion Board ..........69 Table 40: Carrier Board Generated Signal Pin Assignment for the phyCORE-LPC3180 / Carrier Board / Expansion Board....70 Table 41: Unused Pins on the phyCORE-LPC3180 / Carrier Board / Expansion Board ................70 © PHYTEC America LLC 2007...

  • Page 9: Preface

    Electro Magnetic Directives. Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems. The phyCORE-LPC3180 is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC...

  • Page 10: Introduction

    User’s Manual or datasheet. The descriptions in this manual are based on the NXP Semiconductors (founded by Philips) LPC3180. No description of compatible microcontroller derivative functions is included, as such functions are not relevant for the basic functioning of the phyCORE-LPC3180. © PHYTEC America LLC 2007...
  • Page 11 C interfaces (1.8V & 3.0V) • SD card interface with DMA • One high speed capture port • Dedicated GPI, GPO, and GPIO pins at 1.8V and 3.0V Please contact PHYTEC for more information about additional module configurations. © PHYTEC America LLC 2007 L-681e_3...

  • Page 12: Block Diagram

    CTRL & REG. VCC = 3.0V POWER 1.8V DC-DC 1.2V REGULATORS ADJ. 0.9V-1.2V VDD_CORE /RESET IN SUPERVISOR WATCHDOG /RESET RESET I²C 32KB EEPROM KEYBOARD KEYBOARD SD Card SD Card GPIO/GPI/GPO GPIO/GPI/GPO Figure 1: Block Diagram phyCORE-LPC3180 © PHYTEC America LLC 2007 L-681e_3...

  • Page 13: View Of The Phycore-Lpc3180

    Introduction 1.2 V CORE-LPC3180 IEW OF THE PHY Figure 2: Top View of the phyCORE-LPC3180 (controller side) © PHYTEC America LLC 2007 L-681e_3...

  • Page 14: Figure 3: Bottom View Of The Phycore-Lpc3180 (Connector Side)

    Figure 3: Bottom View of the phyCORE-LPC3180 (connector side) © PHYTEC America LLC 2007 L-681e_3...

  • Page 15: Pin Description

    The upper left-hand corner of the numbered matrix (pin 1A) is thus covered with the corner of the phyCORE-LPC3180 marked with a white triangle. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.

  • Page 16: Figure 4: Pinout Of The Phycore-Connector (Top View, With Cross Section Insert)

    Please refer to the NXP Semiconductors phyCORE-LPC3180 User’s Manual/Data Sheet for details on the functions and features of controller signals and port pins.

  • Page 17: Table 1: Pinout Of The Phycore-Connector X200

    USB TX data / D- receive pin of the µC /USB_OE_TP USB transmit enable for DAT / SE0 pin of the µC USB_I2C_SDA C SDA pin of the µC for ISP1301 USB transceiver TST_CLK2 Test clock output pin of the µC © PHYTEC America LLC 2007 L-681e_3...
  • Page 18 Not connected Unused Not connected Unused Not connected Unused Ground 0V Not connected Unused Not connected Unused Not connected Unused Not connected Unused Ground 0V Not connected Unused Not connected Unused Not connected Unused © PHYTEC America LLC 2007 L-681e_3...
  • Page 19 TEST pin of the µC SYSCLKEN SYSCLKEN pin of the µC Ground 0V RTCK JTAG RTCK pin of the µC JTAG TMS pin of the µC /TRST JTAG /TRST pin of the µC Not connected Unused © PHYTEC America LLC 2007 L-681e_3...
  • Page 20 Unused Not connected Unused Ground 0V Not connected Unused Not connected Unused Not connected Unused USB_ADR/PSW ADR/PSW pin of the ISP1301 USB transceiver Ground 0V Not connected Reserved for future use, do not connect. © PHYTEC America LLC 2007 L-681e_3...
  • Page 21 Pin Description X200C IGNAL ESCRIPTION 3.0V power input to the phyCORE-LPC3180 3.0V power input to the phyCORE-LPC3180 Ground 0V Not connected Unused Not connected Unused VBAT 3.0V battery power supply input for the µC’s RTC Ground 0V Not connected Unused General purpose input pin 1 of the µC / /SERVICE...
  • Page 22 Not connected Unused AGND Analog Ground (floating, not connected to GND) ADIN0 ADIN0 pin of the µC (input 0 to ADC) ADIN2 ADIN2 pin of the µC (input 2 to ADC) Not connected Unused © PHYTEC America LLC 2007 L-681e_3...
  • Page 23 Pin Description X200D IGNAL ESCRIPTION 3.0V power input to the phyCORE-LPC3180 3.0V power input to the phyCORE-LPC3180 Ground 0V Not connected Unused Not connected Unused Regulated battery / VCC output voltage to the µC’s RTC power supply pins Not connected...
  • Page 24 U2_HCTS_RS232 transceiver RS-232 level output from the ADM3307 RS-232 U2_HRTS_RS232 transceiver ADIN1 ADIN1 pin of the µC (input 1 to ADC) AGND Analog Ground (not connected to GND) VDDad28_ext VDD_AD28 pin of the µC © PHYTEC America LLC 2007 L-681e_3...

  • Page 25: Jumpers

    Jumpers UMPERS For configuration purposes, the phyCORE-LPC3180 has 18 solder jumpers, some of which have been installed prior to delivery. Figure 5 illustrates the numbering of the solder jumper pads, while Figure 6 and Figure 7 indicate the location of the solder jumpers on the board. All but two solder jumpers are located on the top side of the module (opposite side of connectors).

  • Page 26: Figure 6: Location Of The Jumpers (Top View)

    Figure 6: Location of the Jumpers (Top View) © PHYTEC America LLC 2007 L-681e_3...

  • Page 27: Figure 7: Location Of The Jumpers (Bottom View)

    Jumpers Figure 7: Location of the Jumpers (Bottom View) © PHYTEC America LLC 2007 L-681e_3...

  • Page 28: Table 2: Jumper Settings

    Leaving U408 WDI input disconnected will disable the watchdog feature when in extended mode (see J400) These jumpers are provided as test access points to determine currents supplied by their respective voltage regulators. Removing any of these jumper will result in failed module operation. © PHYTEC America LLC 2007 L-681e_3...

  • Page 29: Figure 8: Default Jumper Settings On The Phycore-Lpc3180 (Top Side)

    6.3.1 from write access Figure 8: Default Jumper Settings on the phyCORE-LPC3180 (Top Side) Switchover from VCC to VBAT is automatic in this setting when the battery control and supply circuitry is populated on the module (default, but optional) © PHYTEC America LLC 2007...

  • Page 30: Figure 9: Default Jumper Settings On The Phycore-Lpc3180 (Bottom Side)

    Figure 9: Default Jumper Settings on the phyCORE-LPC3180 (Bottom Side) © PHYTEC America LLC 2007 L-681e_3...

  • Page 31: J503 Mcko Signal

    AGND plane and pins (analog ground). The AGND pins can be found at the phyCORE-connector pins X200D44, D49, C42, and C47. The nominal value of AGND should be 0V. It is not permissible to set the negative supply reference below ground (0V). © PHYTEC America LLC 2007 L-681e_3...

  • Page 32: Power Requirements

    If you choose not to use a battery with the phyCORE-LPC3180 then either (1) jumper J506 should be set to the 2 + 3 position to connect the LPC3180’s RTC power pins to the 1.2V supply generated on the module (see section 4.1.1 for details on setting J506), or (2) VBAT should be connected to VCC...

  • Page 33: Real Time Clock And Sram Power Source (J506)

    OLTAGE UPERVISION The phyCORE-LPC3180 comes equipped with a triple voltage supervisor IC located at U409. This voltage supervisor is responsible for monitoring the 3.0V supplied to the module through the phyCORE-connector as well as the 1.8V and 1.2V fixed supplies generated on the module. In the...

  • Page 34: System Configuration

    YSTEM ONFIGURATION For operation of the phyCORE-LPC3180 several parts of the system should be initialized. Although very little initialization needs to take place for the most basic operation, it is typical that the following interfaces should be initialized: 1. Clock Generation and Power 2.

  • Page 35: Figure 10: Small Page Slc Nand Flash Structure

    SLC NAND Flash device used on the phyCORE- LPC3180 is presented. The external SLC NAND Flash used on the phyCORE-LPC3180 is a "small page" device consisting of "blocks" and "pages" of data. The NAND Flash is divided into blocks which are 16kB in size. Each block consists of 32 pages which are 512 bytes in size + 16 bytes of "spare"...
  • Page 36 At this point the primary application is running. For most applications not involving an operating system this is all that is needed. It is possible that this application could be yet another boot loader such U-Boot that is responsible for booting Linux. © PHYTEC America LLC 2007 L-681e_3...

  • Page 37: Boot Modes

    X200C9. This signal must be maintained at a HIGH or LOW level after a reset occurs to latch the boot mode properly. Internally on the phyCORE-LPC3180 this pin is pulled up, selecting the NAND Flash boot mode after a reset. Optionally this signal can be connected to GND to select UART5 boot mode.

  • Page 38: Memory Model

    YSTEM EMORY The phyCORE-LPC3180 provides three types of on-board memory: • SDR SDRAM: from 16MB to 64MB • SLC NAND Flash: from 32MB to 128MB • EEPROM: from 1KB to 32KB It should be noted that both the SDR SDRAM and the NAND Flash have dedicated memory buses to the LPC3180 microcontroller.

  • Page 39: System Memory

    The LPC3180 is capable of addressing a single RAM bank located at memory address 0x8000 0000 and extending to 0x9FFF FFFF. It should be noted that this is beyond what the phyCORE-LPC3180 supplies for on-board memory. Refer to Table 8 for permissible SDRAM memory access ranges.

  • Page 40: Nand Flash Write Protection Control (J604)

    * = Default setting 6.4 I²C EEPROM (U601) The phyCORE-LPC3180 is populated with a Microchip 24FC256 non-volatile 32KB EEPROM (U601) with an I²C interface to store configuration data or other general purpose data. This device is accessed through I²C port 1 on the LPC3180. The serial clock signal and serial data signal for I²C port 1 are made available at the phyCORE-connector as I2C1_SDA on X200D32 and I2C1_SCL on X200C31.

  • Page 41: Setting The Eeprom Lower Address Bits (J600, J601, J602)

    The following configurations are possible: Table 12: J603, EEPROM Write Protection States EEPROM W J603 RITE ROTECTION TATE Write Access Allowed closed* Write Protected open * = Default setting © PHYTEC America LLC 2007 L-681e_3...

  • Page 42: Sibl, U-Boot And Linux

    OOT AND INUX With the presence of a full MMU the phyCORE-LPC3180 is capable of running a full featured version of Linux. As of the printing of this manual the phyCORE-LPC3180 Linux BSP supports Linux 2.6.10. Running Linux requires four separate pieces of software to reside in NAND Flash: (1) SIBL (Secondary Boot Loader), (2) U-Boot, (3) the Linux kernel image, and (4) the Linux file system.

  • Page 43: Serial Interfaces

    RxD line of the transceiver is connected to the TxD line of the COM port; while the TxD line is connected to the RxD line of the COM port. The Ground potential of the phyCORE-LPC3180 circuitry needs to be connected to the applicable Ground pin on the COM port as well.

  • Page 44: Usb Transceiver (U300)

    Termination resistors and capacitors have already been populated on the phyCORE-LPC3180. A Vbus capacitor of 4.7uF has also been placed on the phyCORE-LPC3180. It should be noted that the maximum Vbus capacitance a USB OTG device can add to the bus is 6.5uF. Therefore, adding anything but a small capacitor value of 0.1uF external to the phyCORE-LPC3180 on Vbus is not...

  • Page 45: Processor Independent Watchdog (U408)

    NDEPENDENT ATCHDOG In addition to the LPC3180’s on-chip watchdog, the phyCORE-LPC3180 comes equipped with a MAX6301 processor independent watchdog located at U408. This processor independent watchdog is disabled by factory default configuration. To disable the MAX6301 the WDI input must be at high impedance, and the operation mode must be set to extended mode.

  • Page 46: Interfacing The Wdi Watchdog Input (J401)

    IGNAL ONFIGURATION Processor independent watchdog U408 WDI input open* pin disconnected from µC’s GPO_4 output pin Processor independent watchdog U408 WDI input closed pin connected to µC’s GPO_4 output pin * = Default setting © PHYTEC America LLC 2007 L-681e_3...

  • Page 47: Debug Interface X201

    EBUG NTERFACE The phyCORE-LPC3180 is equipped with a JTAG interface for downloading program code into the external Flash, internal controller RAM or for debugging programs currently executing. The JTAG interface also allows access to the Embedded Trace Buffer (ETB) and associated configuration registers.

  • Page 48: Figure 12: Jtag Interface X201 (Bottom View)

    Pin 2 of the JTAG connector is marked by a number two on the controller side of the module. Note: The JTAG connector X201 only populates phyCORE-LPC3180 modules with order code PCM-031-D. This version of the phyCORE module is included in all Rapid Development Kits (order code KPCM-031).

  • Page 49: Table 16: Jtag Connector X201 Signal Assignment

    *Note: Row A is on the controller side of the module and row B is connector side of the module The phyCORE-LPC3180 Carrier Board provides an industry standard 2.54mm pitch 20 pin JTAG connector at X202. See section 13.2.14 for details. PHYTEC also offers 2.00mm to 2.54mm JTAG adapter cables (part# WF-039-ARM).

  • Page 50: Technical Specifications

    ECHNICAL PECIFICATIONS The physical dimensions of the phyCORE-LPC3180 are represented in Figure 13. The module's profile is approximately 7.2 mm thick, with a maximum component height of 2.6 mm on the bottom (connector) side of the PCB and approximately 3.0 mm on the top (microcontroller) side. The board itself is approximately 1.6 mm thick.
  • Page 51 VCC = 3.0 V, VBAT = 3.0V, VCC 3.0 V/90mA typical 32MB NAND, 32MB SDRAM @ 104MHz, 208MHz, most interfaces & clocking domains enabled These specifications describe the standard configuration of the phyCORE-LPC3180 as of the printing of this manual. © PHYTEC America LLC 2007 L-681e_3...

  • Page 52: Hints For Handling The Phycore-Lpc3180

    Overheating the board can cause the solder pads to loosen, rendering the module inoperable. Carefully heat neighboring connections in pairs. After a few alternations, components can be removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and loosen the bonds. © PHYTEC America LLC 2007 L-681e_3...

  • Page 53: The Phycore-Lpc3180 On The Phycore-Lpc3180 Carrier Board

    PHYTEC Single Board Computer (SBC) modules. Carrier Boards are designed for evaluation, testing and prototyping of PHYTEC Single Board Computers in laboratory environments prior to their use in customer designed applications.

  • Page 54: Table 18: Carrier Board Buttons

    D400 User LED #1 (red) 13.2.8 D401 User LED #2 (red) D402 User LED #3 (green) D403 User LED #4 (green) Table 20: Carrier Board Potentiometers OTENTIOMETERS ESCRIPTION ECTION R313 A/D optional input 13.2.10 © PHYTEC America LLC 2007 L-681e_3...

  • Page 55: Figure 14: Component Locations On The Phycore-Lpc3180 Development Board

    GPIO expansion port connector X201. As an accessory a GPIO expansion board (part # PCM-989) is made available through PHYTEC to mate with the X201 connector on the phyCORE-LPC3180 Carrier Board. This expansion board provides a patch field for easy access to all signals, and additional board space for testing and prototyping.

  • Page 56: Jumpers On The Phycore-Lpc3180 Carrier Board

    ARRIER OARD The phyCORE-LPC3180 Carrier Board comes preconfigured with 2 solder jumpers (J) and 13 removable jumpers (JP). The jumpers allow the user flexibility of rerouting a limited amount of signals for development constraint purposes. Table 21 below lists the 2 solder jumpers and 12 removable jumpers, their default positions, and their functions in each position.
  • Page 57 If J300 is not in its default position of 2 + 3 then JP304’s position becomes a don’t care. Although UART5 boot mode is selected, the LPC3180 boot ROM software will boot to NAND Flash if no code is downloaded through UART5 within a timeout period of 1 second. © PHYTEC America LLC 2007 L-681e_3...

  • Page 58: Figure 16: Location Of The Jumpers (View Of The Component Side)

    Figure 16: Location of the Jumpers (View of the Component Side) Figure 16 shows the location of the jumpers on the phyCORE-LPC3180 Carrier Board. © PHYTEC America LLC 2007 L-681e_3...

  • Page 59: Figure 17: Default Jumper Settings Of The Phycore-Lpc3180 Carrier Board (J300, Jp302-304)

    Carrier Board Figure 17: Default Jumper Settings of the phyCORE-LPC3180 Carrier Board (J300, JP302-304) Figure 18: Default Jumper Settings of the phyCORE-LPC3180 Carrier Board (JP300-301, JP307-311, JP400-403) © PHYTEC America LLC 2007 L-681e_3...

  • Page 60: Figure 19: Default Jumper Settings Of The Phycore-Lpc3180 Carrier Board (Jp305-Jp306)

    Figure 17, Figure 18, and Figure 19 show the factory default jumper settings for operation of the phyCORE-LPC3180 Carrier Board with the standard phyCORE-LPC3180. Jumper settings for other functional configurations of the phyCORE-LPC3180 module mounted on the Carrier Board are described in detail in section 13.2.

  • Page 61: Carrier Board

    The required current load capacity of the power supply depends on the specific configuration of the phyCORE-LPC3180 mounted on the Carrier Board as well as whether an optional expansion board is connected to the Carrier Board. An adapter with a minimum supply of 500mA is recommended.

  • Page 62: Accessing Uart5 Through Socket P300A

    See section 8.1 RS-232 Transceivers (U301, U302) for applicable UART data rates. P300B can be connected directly to the RS-232 port on a PC with a standard extension RS-232 cable (not a crossover cable). © PHYTEC America LLC 2007 L-681e_3...

  • Page 63: Sd Card Interface At Connector X300

    NTERFACE AT ONNECTOR Connector X300 provides an interface for a compatible SD card. The phyCORE-LPC3180 Carrier Board supplies additional card detection and power control circuitry to the SD card interface. Four configuration jumpers are supplied for card detection, write protect detection, SD card power source, and SD card power control.

  • Page 64: User Buttons S302 And S303

    D400, D401, D402, D403 User LEDs D400, D401, D402, and D403 are provided on the phyCORE-LPC3180 Carrier Board as general purpose LEDs for software testing or other uses. Four jumpers provide routing control over LED control source. The four jumpers have the following functions: NOTE: See footnote in Table 21 for additional comments on this function.

  • Page 65: Accessing The Usb Through Connectors X301, X302, And X303

    (X303). All three USB connectors are connected to the USB signals at once, however, only one may be used at a time. There is only one USB interfaces on the phyCORE-LPC3180 and as such, only one connector at a time is applicable.

  • Page 66: Battery Connector Bat300

    The mounting space BAT300 (see PCB stencil) is provided for connection of a battery that buffers the RTC on the phyCORE-LPC3180. In the event of a VCC operating voltage failure the RTC is automatically supplied with power from the connected battery. The optional battery required for the RTC buffering (refer to section 4.1) is available through PHYTEC (order code BL-011).

  • Page 67: Keyboard Connector At X203

    Semiconductors' LPC3180 User Manual for a detailed explanation of interfacing the keyboard port. Table 24: Keyboard Connector X203 Signal Assignment IGNAL IGNAL KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_COL5 GPI_8/COL6/BUSY GPI_9/KEY_COL7 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4 KEY_ROW5 GPIO_2/KEY_ROW6 GPIO_3/KEY_ROW7 © PHYTEC America LLC 2007 L-681e_3...

  • Page 68: Debug Interface X202

    EBUG NTERFACE In addition to the JTAG debug connector available on the phyCORE-LPC3180, the phyCORE- LPC3180 Carrier Board also extends these signals to a 20 pin, 2.54mm pitch industry standard connection interface at X202. Pin 1 on the Carrier Board is marked with a clipped corner as depicted in Figure 22 below.

  • Page 69: Pin Assignment Summary Of The Phycore, The Expansion Bus And The Patch Field

    ATCH IELD As described in section 13.1 all signals from the phyCORE-LPC3180 extend in a strict 1:1 assignment to the Expansion Bus connector X201 on the Carrier Board. These signals, in turn, are routed in a similar manner to the patch field on an optional GPIO expansion board that mounts to the Carrier Board at X201.
  • Page 70 Figure 24: Pin Assignment Scheme of the Patch Field on the Optional GPIO Expansion Board The pin assignment on the phyCORE-LPC3180, in conjunction with the Expansion Bus (X201) on the Carrier Board and the patch field on the optional GPIO expansion board is detailed in the following tables.

  • Page 71: Table 26: Gpi Pin Assignment For The Phycore-Lpc3180 / Carrier Board / Expansion Board

    Carrier Board Table 26: GPI Pin Assignment for the phyCORE-LPC3180 / Carrier Board / Expansion Board phyCORE M IGNAL ODULE XPANSION ATCH IELD GPI_0 GPI_1//SERVICE GPI_2 GPI_3 GPI_4/SPI1_BUSY GPI_5 GPI_6/HSTIM_CAPTURE GPI_7 GPI_8/KEY_COL6/SPI2_BUSY GPI_9/KEY_COL7 GPI_10/U4_RX GPI_11 © PHYTEC America LLC 2007...

  • Page 72: Table 27: Gpo Pin Assignment For The Phycore-Lpc3180 / Carrier Board / Expansion Board

    Table 27: GPO Pin Assignment for the phyCORE-LPC3180 / Carrier Board / Expansion Board phyCORE M IGNAL ODULE XPANSION ATCH IELD GPO_0/TST_CLK1 GPO_1 GPO_2 GPO_3 GPO_4 GPO_5 GPO_6 GPO_7 GPO_8 GPO_9 GPO_10 GPO_11 GPO_12 GPO_13 GPO_14 GPO_15 GPO_16 GPO_17...

  • Page 73: Table 29: Spi Pin Assignment For The Phycore-Lpc3180 / Carrier Board / Expansion Board

    M IGNAL ODULE XPANSION ATCH IELD SPI1_CLK SPI1_DATIN SPI1_DATIO SPI2_CLK SPI2_DATIN SPI2_DATIO Table 30: SD Card Pin Assignment for the phyCORE-LPC3180 / Carrier Board / Expansion Board SD CARD phyCORE M IGNAL ODULE XPANSION ATCH IELD MS_CLK MS_BS MS_DIO0 MS_DIO1...

  • Page 74: Table 32: Jtag/Debug Pin Assignment For The Phycore-Lpc3180 / Carrier Board / Expansion Board

    JTAG/DEBUG Pin Assignment for the phyCORE-LPC3180 / Carrier Board / Expansion Board JTAG/DEBUG phyCORE M IGNAL ODULE XPANSION ATCH IELD RTCK /TRST Table 33: System Pin Assignment for the phyCORE-LPC3180 / Carrier Board / Expansion Board SYSTEM phyCORE M IGNAL ODULE XPANSION ATCH IELD CLKIN MCKO GPI_1//SERVICE...

  • Page 75: Table 34: A/D Pin Assignment For The Phycore-Lpc3180 / Carrier Board / Expansion Board

    Carrier Board Table 34: A/D Pin Assignment for the phyCORE-LPC3180 / Carrier Board / Expansion Board phyCORE M IGNAL ODULE XPANSION ATCH IELD ADIN0 ADIN1 ADIN2 VDDad28_ext Table 35: PWM Pin Assignment for the phyCORE-LPC3180 / Carrier Board /...

  • Page 76: Table 37: Uart Pin Assignment For The Phycore-Lpc3180 / Carrier Board / Expansion Board

    Table 37: UART Pin Assignment for the phyCORE-LPC3180 / Carrier Board / Expansion Board UART phyCORE M IGNAL ODULE XPANSION ATCH IELD U1_TX U1_RX U2_TX U2_RX U2_HCTS GPO_23/U2_HRTS U2_TX_RS232 U2_RX_RS232 U2_HCTS_RS232 U2_HRTS_RS232 U3_TX U3_RX U3_TX_RS232 U3_RX_RS232 GPO_21/U4_TX GPI_10/U4_RX U5_TX...

  • Page 77: Table 38: Keyboard Pin Assignment For The Phycore-Lpc3180 / Carrier Board / Expansion Board

    Carrier Board Table 38: Keyboard Pin Assignment for the phyCORE-LPC3180 / Carrier Board / Expansion Board KEYBOARD phyCORE M IGNAL ODULE XPANSION ATCH IELD KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_COL5 GPI_8/KEY_COL6/SPI2_BUSY GPI_9/KEY_COL7 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4 KEY_ROW5 GPIO_2/KEY_ROW6...

  • Page 78: Table 40: Carrier Board Generated Signal Pin Assignment For The Phycore-Lpc3180 / Carrier Board / Expansion Board

    LED1_C LED2_C LED3_C LED4_C ADC_VADJ BUTTON1 /BUTTON1 BUTTON2 /BUTTON2 Table 41: Unused Pins on the phyCORE-LPC3180 / Carrier Board / Expansion Board UNUSED PINS phyCORE IGNAL XPANSION ATCH IELD ODULE 4D, 5D,7D, 4D, 5D, 7D, 4C, 5C, 8C, 51D, 52D,...

  • Page 79: Revision History

    Version Changes in this manual numbers 11-Apr-2006 Manual L-681e_1 First draft, Preliminary documentation. PCM-031 Describes the phyCORE-LPC3180 only PCB# 1247.0 PCM-976 PCB# 1248.0 24-Nov-2006 Manual L-681e_2 First release version describing PCB revision 1247.1 and 1248.1. PCM-031 Section 5, System Configuration expanded.

  • Page 80: Component Placement Diagram

    15 C OMPONENT LACEMENT IAGRAM Figure 25: phyCORE-LPC3180 Component Placement, Top View © PHYTEC America LLC 2007 L-681e_3...
  • Page 81 Component Placement Diagram Figure 26: phyCORE-LPC3180 Component Placement, Bottom View © PHYTEC America LLC 2007 L-681e_3...
  • Page 82 PPENDIX Example SDRAM initialization code for the phyCORE-LPC3180 can be downloaded from the following URL: www.phytec.com/zip/download/LPC3180_SDRAM_Init.zip © PHYTEC America LLC 2007 L-681e_3...

  • Page 83: Index

    ECC..........34 JP311........56 EEPROM......30, 32 JP400........56 EEPROM Write Protection ..33 JP401........56 Embedded Trace Buffer ...39 JP402........56 EMC ...........1 JP403........56 Expansion Bus ......61 JTAG Interface ......39 Features ........3 Jumper Configuration....48 File System ......34 Keyboard Connector ....59 © PHYTEC America LLC 2007 L-681e_3...
  • Page 84 USB Transceiver ......36 S301.........56 User Button ......56 S302........46, 56 User LEDs........56 S303.........46 VBAT........24 SD Card Interface ....55 Vbus.........36 SD Card Power ......55 VDD_1V2 .........25 SDR SDRAM......30, 31 VMMC ........55 SDRAM ........31 Voltage Supervision ....25 © PHYTEC America LLC 2007 L-681e_3...
  • Page 85 Watchdog .........37 X203........45, 59 on-chip........37 X300........45, 55 processor independent...37 X301........45, 57 Timeout Period.......37 X302........45, 57 WDI ........37, 38 X303........45, 57 Weight ........43 X304........45, 55 X200.........45 X305.........45 X201........39, 45 X306........45, 58 X202........45, 60 X307........45, 58 © PHYTEC America LLC 2007 L-681e_3...
  • Page 86 © PHYTEC America LLC 2007 L-681e_3...
  • Page 87 Suggestions for Improvement Document: phyCORE-LPC3180 Hardware Manual Document number: L-681e_3, April 2007 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG...
  • Page 88 Published by © PHYTEC Meßtechnik GmbH 2007 Ordering No. L-681e_3 Printed in Germany...

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