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Phytec phyCORE-Vybrid Hardware Manual

System on module and carrier board
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phyCORE-Vybrid
System on Module and Carrier Board
Hardware Manual
Document No:
L-783e_0
Product No:
PCM-052/PCM-952
SOM PCB No:
1374.0
CB PCB No:
1375.2
Edition: December 11, 2012
A product of a PHYTEC Technology Holding Company

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Summary of Contents for Phytec phyCORE-Vybrid

  • Page 1 System on Module and Carrier Board Hardware Manual Document No: L-783e_0 Product No: PCM-052/PCM-952 SOM PCB No: 1374.0 CB PCB No: 1375.2 Edition: December 11, 2012 A product of a PHYTEC Technology Holding Company...
  • Page 2 PHYTEC America LLC reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.

  • Page 3: Table Of Contents

    Part I: PCM-052/phyCORE-Vybrid System on Module ........
  • Page 4 14 phyCORE-Vybrid SOM Connectivity ........

  • Page 5: List Of Tables

    Part I: PCM-052/phyCORE-Vybrid System on Module ........
  • Page 6 Fig. 1-1. phyCORE-Vybrid Block Diagram ......... . . 4 Fig. 1-2. Top View of the phyCORE-Vybrid (Controller Side)......5 Fig.

  • Page 7: Conventions, Abbreviations, And Acronyms

    PHYTEC Extension Board PMIC Power Management Integrated Circuit Power over Ethernet Package on Package Power-on reset Real-time clock Surface mount technology System on Module; used in reference to the PCM-052/phyCORE-Vybrid System on Module © PHYTEC America LLC 2012...

  • Page 8: Table 1-2. Types Of Signals

    5V tolerant input with pull-down 5V_PD LVDS Differential line pairs 100 Ohm LVDS Pegel LVDS Differential 90 Ohm Differential line pairs 90 Ohm DIFF90 Differential 100 Ohm Differential line pairs 100 Ohm DIFF100 Analog Analog input or output Analog © PHYTEC America LLC 2012...
  • Page 9 PHYTEC System on Modules (SOMs) are designed for installation in electrical appliances or, combined with the PHYTEC Carrier Board, can be used as dedicated Evaluation Boards (for use as a test and prototype platform for hardware/software development) in laboratory environments.
  • Page 10 Product Change Management In addition to our HW and SW offerings, the buyer will receive a free obsolescence maintenance service for the HW provided when purchasing a PHYTEC SOM. Our Product Change Management Team of developers is continuously processing all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts which are being used in our products.

  • Page 11: Part I: Pcm-052/Phycore-Vybrid System On Module

    Part I: PCM-052/phyCORE-Vybrid System on Module Part 1 of this three part manual provides detailed information on the phyCORE-Vybrid System on Module (SOM) designed for custom integration into customer applications. The information in the following chapters is applicable to the 1374.0 PCB revision of the phyCORE-Vybrid SOM.

  • Page 12: Introduction

    • Dual USB OTG 2.0 High-Speed Controller with PHY 1. The maximum memory size listed is as of the printing of this manual. Please contact PHYTEC for more information about additional, or new module configurations available. © PHYTEC America LLC 2012...

  • Page 13: Minimum Requirements To Operate The Phycore-Vybrid

    -40 to 85 C operating temperature range 1.2 Minimum Requirements to Operate the phyCORE-Vybrid Basic operation of the phyCORE-Vybrid requires a 3.3V +-5% supply voltage with at least 1.0A current capacity. Connect power and ground to the following pins on connector X1 to power the SOM: 3.3V: X1-1C, 2C, 1D, 2D...

  • Page 14: Block Diagram

    Part I, Chapter 1: Introduction L-783e_0 1.3 Block Diagram Fig. 1-1. phyCORE-Vybrid Block Diagram © PHYTEC America LLC 2012...

  • Page 15: View Of The Phycore-Vybrid

    Part I, Chapter 1: Introduction L-783e_0 1.4 View of the phyCORE-Vybrid Fig. 1-2. Top View of the phyCORE-Vybrid (Controller Side) © PHYTEC America LLC 2012...

  • Page 16: Fig. 1-3. Bottom View Of The Phycore-Vybrid (Connector Side)

    Part I, Chapter 1: Introduction L-783e_0 Fig. 1-3. Bottom View of the phyCORE-Vybrid (Connector Side) © PHYTEC America LLC 2012...

  • Page 17: Pin Description

    All controller signals extend to surface mount technology (SMT) connectors (0.5 mm) lining two sides of the module (referred to as the phyCORE-Connector). This allows the phyCORE-Vybrid to be plugged into any target application like a "big chip."...

  • Page 18: Table 2-1. Pinout Of The Phycore-Connector X1, Row A

    VFx00 datasheet or TRM for more information about alternative functions. In order to utilize a spe- cific pin's alternative function the corresponding registers must be configured within the appropriate driver of the BSP. To support all features of the phyCORE-Vybrid Carrier Board a few changes have been made in the BSP delivered with the module.
  • Page 19 MCU_PTD6 VDD_3V3 SD Card Detect (SDCD) Ground 0 V MCU_PTC4 VDD_3V3 RMII0 Receive Data 0 MCU_PTC5 VDD_3V3 RMII0 Receive Error MCU_PTC6 VDD_3V3 RMII0 Transmit Data 1 MCU_PTC7 VDD_3V3 RMII0 Transmit Data 0 Ground 0 V © PHYTEC America LLC 2012...

  • Page 20: Table 2-2. Pinout Of The Phycore-Connector X1, Row B

    VDD_3V3 GPIO MCU_PTB20 SPI0 Master-Out-Slave-In (MOSI) Ground 0 V MCU_PTB25 VDD_3V3 NAND Flash chip enable MCU_PTB26 VDD_3V3 GPIO MCU_PTB27 VDD_3V3 NAND Flash read enable MCU_PTB28 VDD_3V3 GPIO Ground 0 V MCU_PTD20 VDD_3V3 NAND Flash IO4 © PHYTEC America LLC 2012...
  • Page 21 RMII1 Receive Data 1 MCU_PTC17 VDD_3V3 RMII1 Transmit Enable MCU_PTA6 VDD_3V3 RMII1 clock MCU_PTA7 VDD_3V3 SD write-protect Ground 0 V ADC0SE8 Analog VDD_3V3 Analog signal ADC0SE9 Analog VDD_3V3 Analog signal ADC1SE8 Analog VDD_3V3 Analog signal © PHYTEC America LLC 2012...

  • Page 22: Table 2-3. Pinout Of The Phycore-Connector X1, Row C

    DIFF90 VDD_3V3 USB0 data minus Ground 0 V ETH0_RXM LVDS VDD_3V3 Ethernet0 receive data minus ETH0_RXP LVDS VDD_3V3 Ethernet0 receive data plus ETH0_TXM LVDS VDD_3V3 Ethernet0 transmit data minus ETH0_TXP LVDS VDD_3V3 Ethernet0 transmit data plus © PHYTEC America LLC 2012...
  • Page 23 Display green 4 MCU_PTE18 VDD_3V3 Display green 5 MCU_PTE19 VDD_3V3 Display green 6 MCU_PTE20 VDD_3V3 Display green 7 Ground 0 V MCU_PTE25 VDD_3V3 Display blue 4 MCU_PTE26 VDD_3V3 Display blue 5 MCU_PTE27 VDD_3V3 Display blue 6 © PHYTEC America LLC 2012...

  • Page 24: Table 2-4. Pinout Of The Phycore-Connector X1, Row D

    Ground 0 V ETH1_LED0 VDD_3V3 Ethernet1 LED 0 ETH1_LED1 VDD_3V3 Ethernet1 LED 1 MCU_PTA12 VDD_3V3 Trace clock MCU_PTA16 VDD_3V3 Trace Data 0 Ground 0 V MCU_PTA21 VDD_3V3 Trace data 5 MCU_PTA22 VDD_3V3 Trace data 6 © PHYTEC America LLC 2012...
  • Page 25 VDD_3V3 Display green 3 Ground 0 V MCU_PTE21 VDD_3V3 Display blue 0 MCU_PTE22 VDD_3V3 Display blue 1 MCU_PTE23 VDD_3V3 Display blue 2 MCU_PTE24 VDD_3V3 Display blue 3 Ground 0 V MCU_PTE28 VDD_3V3 Display blue 7 © PHYTEC America LLC 2012...

  • Page 26: Jumpers

    Part I, Chapter 3: Jumpers L-783e_0 3 Jumpers For configuration purposes the phyCORE-Vybrid has three solder jumpers which have been installed prior to delivery. Figure 3-1 illustrates the jumper pad numbering scheme for reference when altering jumper settings on the board. Three and four position jumpers have pin 1 marked with a GREEN pad. The beveled edge in the silk-screen around the jumper indicates the location of pin 1.

  • Page 27: Jumper Settings

    (0 Ohms, 10k Ohms, etc.). All jumpers are 0805 package or 0402 package with a 1/8W or better power rating. A detailed description of each solder jumper can be found in the applicable chapter listed in the table. © PHYTEC America LLC 2012...

  • Page 28: Table 3-1. Som Jumper Settings

    Sets EEPROM lower address bit A1 = 0 Sets EEPROM lower address bit A2 = 1 0R (0402) 7.4.1 Sets EEPROM lower address bit A2 = 0 The EEPROM is writeable 0R (0402) 7.4.2 OPEN The EEPROM is write-protected © PHYTEC America LLC 2012...

  • Page 29: Power

    Part I, Chapter 4: Power L-783e_0 4 Power The phyCORE-Vybrid operates off of a single 3.3V system power supply. An overview of the power design is shown in the figure below. Fig. 4-1. phyCORE-Vybrid Power Design The following sections of this chapter describe each component of the power design of the phyCORE- Vybrid.

  • Page 30: Ddr3 Power

    The phyCORE-Vybrid includes a voltage supervisor at U1 which asserts the system reset when the voltage of the primary system power is below 3V. For proper operation the phyCORE-Vybrid must be supplied with a voltage source of 3.3V ± 5% with at least 1.0 A capacity at the VDD_3V3 pins on the phyCORE- Connector X1.

  • Page 31: External Rtc

    The RTC is powered via the primary system 3.3V supply during normal operation and via the VBAT power input, if it is present, during power-off. See Chapter 4.4 for detailed information on providing backup power to the RTC via the VBAT power input. © PHYTEC America LLC 2012...

  • Page 32: System Configuration And Booting

    After the reset cycle completes these pins may be used for other purposes. When using these pins for other purposes, make sure their secondary functions are tri-stated, or disabled during the reset cycle to avoid interfering with the latched boot mode. © PHYTEC America LLC 2012...

  • Page 33: System Memory

    Chapter 7.4.1 details on using these jumpers to set the EEPROM's address. 1. The maximum memory size listed is as of the printing of this manual. Please contact PHYTEC for more information about additional, or new module configurations available. © PHYTEC America LLC 2012...

  • Page 34: Setting The Eeprom Lower Address Bits

    The four upper address bits of the I C EEPROM's 7-bit address are fixed at ‘1010.’ Lower address bit A0 is wired to GND. The phyCORE-Vybrid SOM allows the user to configure the lower address bits A1 and A2 with jumpers J1 and J2 respectively.

  • Page 35: Serial Interfaces

    8.1 SCI / RS-232 The phyCORE-Vybrid provides an on-board RS-232 transceiver at U15. This device provides RS-232 voltage level translation for either the SCI1 interface data signals with its RTS/CTS hardware flow control signals, or for both of the SCI1 and SCI2 interface data signals. These SCI and RS-232 signals are available at the phyCORE connector.

  • Page 36: Flexcan

    The VFx00 includes two CAN interfaces. These support bitrates up to 1 MBit/s and are compliant to the FlexCAN3 protocol specification. The phyCORE-Vybrid provides two CAN transceivers at U13 and U14. These transceivers can be used to translate the signal voltages out of the VFx00 to CAN levels and ISO 11898 requirements.

  • Page 37: Technical Specifications

    Part I, Chapter 9: Technical Specifications L-783e_0 9 Technical Specifications The physical dimensions of the phyCORE-Vybrid are presented in Figure 9-1. The module's profile is max. 5.5 mm thick, with a maximum component height of 2.0 mm on the bottom (connector) side of the PCB and approximately 2.5 mm on the top (microcontroller) side.

  • Page 38: Table 9-1. Technical Specifications

    Flash, Ethernet, 450 MHz CPU frequency, 20 °C a. These specifications describe the standard configuration of the phyCORE-Vybrid as of the printing of this manual. b. In order to guarantee reliable functioning of the SOM up to the maximum temperature appropriate cooling measures must be provided.

  • Page 39: Integrating And Handling The Phycore-Vybrid

    At minimum four GND pins should be connected in addition to the four VDD pins used for SOM power (see Chapter 1.2 for details). For maximum EMI performance all GND pins should be connected to a solid ground plane. To facilitate the integration of the phyCORE-Vybrid into your design, the footprint of the phyCORE-Vybrid is shown in Figure 10-1.

  • Page 40: Handling The Phycore-Vybrid

    Besides this hardware manual, other information is available to facilitate the integration of the phyCORE- Vybrid into customer applications: • The design of the phyCORE-Vybrid Carrier Board can be used as a reference for any customer application. Reference schematics are available upon request. •...

  • Page 41: Part Ii: Pcm-952/Phycore-Vybrid Carrier Board

    L-783e_0 Part II: PCM-952/phyCORE-Vybrid Carrier Board Part 2 of this three part manual provides detailed information on the phyCORE-Vybrid Carrier Board and its usage with the phyCORE-Vybrid SOM. The information and all board images in the following chapters are applicable to the 1375.2 PCB revision of the phyCORE-Vybrid Carrier Board.

  • Page 42: Introduction

    The phyCORE-Vybrid Carrier Board is designed for evaluation, testing, and prototyping of PHYTEC SOMs in laboratory environments prior to their use in customer designed applications.
  • Page 43 • Backup battery to power the Real-Time Clock • Reset, power, and user buttons and LEDs The following sections contain information specific to the operation of the phyCORE-Vybrid SOM mounted on the phyCORE-Vybrid Carrier Board. © PHYTEC America LLC 2012...

  • Page 44: Overview Of Peripherals

    L-783e_0 12 Overview of Peripherals Fig. 12-1. Overview of Peripherals The phyCORE-Vybrid Carrier Board is depicted in Figure 11-1. It is equipped with the components and peripherals listed in the tables below. For a more detailed description of each peripheral, refer to the appropriate chapter listed in the applicable table.

  • Page 45: Connectors And Pin Headers

    Part II, Chapter 12: Overview of Peripherals L-783e_0 12.1 Connectors and Pin Headers Fig. 12-2. phyCORE-Vybrid Connectors (Top) Fig. 12-3. phyCORE-Vybrid Connectors (Bottom) © PHYTEC America LLC 2012...

  • Page 46: Table 12-1. Phycore-Vybrid Connectors

    Part II, Chapter 12: Overview of Peripherals L-783e_0 The table below lists the connectors on the phyCORE-Vybrid Carrier Board. Table 12-1. phyCORE-Vybrid Connectors Reference Description Chapter Designator phyCORE-Connectors for SOM connectivity +5 V power input (primary power input, 3 A capacity) Ethernet0 RJ45 connector USB 2.0 Dual Standard-A...

  • Page 47: Buttons And Switches

    12.2 Buttons and Switches Fig. 12-4. Buttons and Switches The phyCORE-Vybrid Carrier Board is populated with four push-button switches and an 8-position DIP- switch. These are essential for the operation of the phyCORE-Vybrid module on the Carrier Board. Figure 12-4 shows their locations, while their functions are described in the tables below.

  • Page 48: User Programmable Push Buttons

    Connects S4 to Vybrid signal MCU_PTB9 12.2.3 Boot Configuration Switch The 8-position DIP switch at S5 provides a way to override the default boot option of the VFx00, which is defined by resistors on the phyCORE-Vybrid SOM. (please refer to Chapter 6 for more information).

  • Page 49: Leds

    Part II, Chapter 12: Overview of Peripherals L-783e_0 12.3 LEDs Fig. 12-5. LEDs The phyCORE-Vybrid Carrier Board is populated with numerous LEDs to indicate the status of various interfaces as well as the input power supply. Figure 12-5 shows the location of the LEDs. Their functions are listed in the table below.

  • Page 50: User Programmable Leds

    Vybrid DAC1 signal when jumper JP23 is installed. Is controlled by the Vybrid processor on the SOM and can be turned on and off by the Vybrid GPIO signal MCU_PTB10 when resistor R138 is installed. © PHYTEC America LLC 2012...

  • Page 51: Jumpers

    The phyCORE Carrier Board comes pre-configured with 22 removable jumpers and 4 solder jumpers. Figure 13-1 provides a detailed view of the phyCORE-Vybrid Carrier Board jumpers and their default settings. The jumpers allow the user flexibility of configuring a limited number of features for development purposes.

  • Page 52: Table 13-1. Jumper Settings And Descriptions

    12.2 OPEN User Button 1 is not connected to the signal MCU_PTB8 JP21 CLOSED User Button 2 is connected to the signal MCU_PTB9 12.2 OPEN User Button 2 is not connected to the signal MCU_PTB9 © PHYTEC America LLC 2012...
  • Page 53 VCC_10V4 is supplied by Q1 CLOSED The audio codec external oscillator OZ1 is enabled The audio codec external oscillator OZ1 is disabled J3, J4 USB1 routes to the PHYTEC Display Connector X30 USB1 routes to the USB1 connector X8 © PHYTEC America LLC 2012...

  • Page 54: Phycore-Vybrid Som Connectivity

    Part II, Chapter 14: phyCORE-Vybrid SOM Connectivity L-783e_0 14 phyCORE-Vybrid SOM Connectivity Fig. 14-1. phyCORE-Vybrid SOM Connectivity to the Carrier Board Connectors X1 on the Carrier Board provide connectivity to the phyCORE SOM and are keyed for proper insertion. Figure 14-1 shows the location of these connectors.

  • Page 55: Power

    Fig. 15-1. Powering Scheme The primary input power of the phyCORE-Vybrid Carrier Board is supplied from the wall adapter jack at X2 (5V with 3A capacity). An alternate 5V input connector at X26 is an optional feature with a 16A capacity.

  • Page 56: Wall Adapter Input

    Vybrid at pin X1-C4. This voltage source supplies the backup voltage domain VBAT of the VFx00 which supplies the RTC and some critical registers when the primary system power, VCC_3V3, is removed. Install jumper JP1=1+2 to connect the VBAT supply to the phyCORE-Vybrid. 15.3 Current Measurement To facilitate current measurement, jumper JP22 is provided as a current measurement access point.

  • Page 57: Ethernet

    This Ethernet PHYs on the SOM support the HP Auto-MDIX function, eliminating the need for considerations of a direct connect LAN cable or a cross-over patch cable. The transceivers detect the TX and RX signals of the connected devices and automatically configure their TX and RX pins accordingly. © PHYTEC America LLC 2012...

  • Page 58: Rs-232

    The X31 pin header provides the SCI2 signals at RS-232 level. Table 17-2 Table 17-1 show the signal locations and descriptions for these connectors. Fig. 17-2. DB-9 RS-232 Connectors P1A and P1B Pin Numbering © PHYTEC America LLC 2012...

  • Page 59: Table 17-1. X10 Pin Descriptions

    UART1 receive signal at RS232 level Not connected Ground Not connected Not connected Not connected Not connected Table 17-2. X31 Pin Descriptions Signal Type Description MCU_PTB6 RS-232 SCI2_TX at RS-232 level Ground 0 V MCU_PTB7 RS-232 SCI2_RX at RS-232 level © PHYTEC America LLC 2012...

  • Page 60: Can (Controller Area Network)

    2. Alternate configuration: the signals route directly from the Vybrid processor to their phyCORE connector pins. To use this configuration, the transceivers must be physically removed from the SOM. Please contact PHYTEC for more information about this configuration option. On the Carrier Board: 1.

  • Page 61: Vcc_Can

    Note that for both CB operating modes the CAN0 transceiver must be removed from the SOM. Please contact PHYTEC for assistance in removing CAN transceviers on the SOM. A summary of the jumper settings for each operating mode is presented in Table 18-1.

  • Page 62: Usb Connectivity

    Each of the USB interfaces has its own voltage supply. LED D16 indicates when VCC_USB0 is powered, and LED D15 indicates when VCC_USB1 is powered. If either of these supplies goes into an over-current condition, the Vybrid will disable both. © PHYTEC America LLC 2012...

  • Page 63: Display

    This connector provides the 3.3V TTL level display signals, power (3.3V), and GND on a 2.54mm pin header for easy access. This connector connects to a low cost display provided by PHYTEC. The display is a 7" TFT panel with a resolution of 800x480 @ 24bpp manufactured by the HTDISPLAY ELECTRON- ICS CO., LTD.

  • Page 64: Display Signals

    Display horizontal sync MCU_PTE20 VCC_3V3 Display green 7 MCU_PTE1 VCC_3V3 Display vertical sync MCU_PTE23 VCC_3V3 Display blue 2 MCU_PTE4 VCC_3V3 Display enable MCU_PTE24 VCC_3V3 Display blue 3 MCU_PTE2 VCC_3V3 Display clock Ground Ground VCC_3V3 VCC_3V3 Power © PHYTEC America LLC 2012...

  • Page 65: Tft Display

    VCC_3V3 Green 4 MCU_PTE16 VCC_3V3 Green 3 MCU_PTE15 VCC_3V3 Green 2 MCU_PTE14 VCC_3V3 Green 1 MCU_PTE13 VCC_3V3 Green 0 MCU_PTE12 VCC_3V3 Red 7 MCU_PTE11 VCC_3V3 Red 6 MCU_PTE10 VCC_3V3 Red 5 MCU_PTE9 VCC_3V3 Red 4 © PHYTEC America LLC 2012...

  • Page 66: Phytec Display Interface

    The Carrier Board provides an LVDS transmitter IC to convert the TTL level signals provided by the Vybrid processor into the LVDS level signals required by the PHYTEC Display Interface. Enables the LVDS transmitter U3 for the PHYTEC Display Interface at X30. To enable the interface, jumper JP4 must be removed.

  • Page 67: Table 20-4. Pdi Connector (X30B) Signal Descriptions

    VCC_3V3 LVDS data channel 1 negative output DISP_LVDS_1+ LVDS VCC_3V3 LVDS data channel 1 positive output Ground DISP_LVDS_2- LVDS VCC_3V3 LVDS data channel 2 negative output DISP_LVDS_2+ LVDS VCC_3V3 LVDS data channel 2 positive output © PHYTEC America LLC 2012...

  • Page 68: Touch Screen

    An 8-bit ADC at U21 on the Carrier Board provides the analog input required for reading a light sensor located on one of the PDI compatible PHYTEC displays. The ADC connects to the Vybrid via I2C2 at address 0x64 (MSB).

  • Page 69: Sd/Mmc

    21 SD/MMC Fig. 21-1. SD/MMC Interface The phyCORE-Vybrid Carrier Board provides a standard Secure Digital Memory SDHC card slot at X9 for connection to SD / MMC cards. Power to the SD interface is supplied by inserting the appropriate card into the SD / MMC connector.

  • Page 70: Audio

    22 Audio Fig. 22-1. Audio Interface The audio interface provides a method of exploring the VFx00's audio capabilities. The phyCORE-Vybrid Carrier Board is populated with a Freescale Semiconductors SGTL5000 audio codec at U12. The SGTL5000 is connected to the VFx00's audio interface to support mono microphone input, stereo headphone output, stereo line out, and stereo line in.

  • Page 71: Table 22-1. Audio Connectors

    Audio devices can be connected at X20, X25, X27 and X28. The audio connectors descriptions are listed Table 22-1. Table 22-1. Audio Connectors Connector Description Stereo line in Mono microphone in Stereo line out Stereo headphone out © PHYTEC America LLC 2012...

  • Page 72: Jtag

    23 JTAG Fig. 23-1. JTAG Connectivity The JTAG interface of the phyCORE-Vybrid is accessible at connectors X16 and X19 on the Carrier Board. This interface is compliant with JTAG specification IEEE 1149.1 and IEEE 1149.7. Provides JTAG signal access with a limited number of trace signals on a 1.27mm header.

  • Page 73: Table 23-2. Jtag Connector X19 Signals

    JTAG Chain Test Data Input MCU_PTA11 VCC_3V3 JTAG Chain Test Mode Select signal MCU_PTA8 VCC_3V3 JTAG Chain Test Clock signal no-connect JTAG Chain Return Test Clock signal MCU_PTA10 VCC_3V3 JTAG Chain Test Data Output SRST VCC_3V3 System Reset © PHYTEC America LLC 2012...

  • Page 74: Trace

    L-783e_0 24 Trace Fig. 24-1. Trace MICTOR Connector X22 is an optional feature which provides direct connectivity to the phyCORE-Vybrid processor Trace interface. This connector does not come standard; it must be special ordered. Table 24-1 shows the signal locations and descriptions on connector X22.
  • Page 75 MCU_PTA27 VCC_3V3 Trace Data 11 no-connect MCU_PTA26 VCC_3V3 Trace Data 10 no-connect MCU_PTA25 VCC_3V3 Trace Data 9 MCU_PTB13 VCC_3V3 Trace Control MCU_PTA24 VCC_3V3 Trace Data 8 MCU_PTA16 VCC_3V3 Trace Data 0 39 - 43 Ground © PHYTEC America LLC 2012...

  • Page 76: K20

    The system can be reset directly with the K20's GPIO signal PTB1, or there are options for putting the system in reset with a jumper across X15 pins. Table 25-1 shows options to put the system in reset with X15 and the JP28 jumper settings to select the target device. © PHYTEC America LLC 2012...

  • Page 77: Table 25-1. K20 Jumper Configurations

    The system is reset with the K20 SPI0 chip select signal K20_SPI0_CS. The system is reset with the K20 GPIO signal K20_GPIO_PTD6 The system is reset while this jumper is installed Select SPI Flash A JP28 Select SPI Flash B © PHYTEC America LLC 2012...

  • Page 78: Tamper

    In addition to routing all four of these signals to the GPIO Expansion Connector, the phyCORE-Vybrid Carrier Board provides test pads TP3 and TP4 on the TAMPER[1:0] signals and jumper JP19 across the TAMPER[3:2] signals.

  • Page 79: Part Iii: Pcm-957/Gpio Expansion Board

    Part 3 of this three part manual provides detailed information on the GPIO Expansion Board and how it enables easy access to most phyCORE-Vybrid SOM signals. The information in the following chapters is applicable to the 1351.0 PCB revision of the GPIO Expansion Board.

  • Page 80: Introduction

    Carrier Board. As an accessory, a GPIO Expansion Board (PCM-957) is made available through PHYTEC to connect to the GPIO Expansion Connectors. This Expansion Board provides a patch field for easy access to signals and additional board space for testing and prototyping.

  • Page 81: Analog Signal Mapping

    VCC_3V3 analog IO DACO1 VCC_3V3 analog IO ADC0SE8 VCC_3V3 analog IO ADC0SE9 VCC_3V3 analog IO ADC1SE8 VCC_3V3 analog IO ADC1SE9 VCC_3V3 analog IO VREFL_ADC VCC_3V3 Analog reference voltage high VREFH_ADC VCC_3V3 Analog reference voltage low © PHYTEC America LLC 2012...

  • Page 82: Control Signal Mapping

    Signal Type Description RESETn VCC_3V3 System reset VDD_1V5_EN VCC_3V3 RESERVED PHYWIRE VCC_3V3 PHYWIRE to the PHYTEC Display Interface TS_WP VCC_3V3 Touch screen wiper contact (5-wire only) for PHYTEC Display Interface NF_WPn VCC_3V3 Write-protect for NAND Flash on SOM CAN_EN VCC_3V3...

  • Page 83: Processor Signal Mapping

    MCU_PTB1 VCC_3V3 Audio Data Out MCU_PTB2 VCC_3V3 Vybrid configuration signal. This signal must be low during system reset MCU_PTB3 VCC_3V3 Display Enable for PHYTEC Display Interface MCU_PTB6 VCC_3V3 SCI2_Tx MCU_PTB7 VCC_3V3 SCI2_Rx MCU_PTB10 VCC_3V3 Interrupt in from the touch-screen controller or control signal out to User LED1.
  • Page 84 VCC_3V3 NAND Flash IO13 MCU_PTD30 27B VCC_3V3 NAND Flash IO14 MCU_PTD31 28B VCC_3V3 NAND Flash IO15 MCU_PTE3 VCC_3V3 GPIO CANL1 VCC_3V3 MCU_PTB16 through CAN transceiver on SOM CANH1 VCC_3V3 MCU_PTB17 through CAN transceiver on SOM © PHYTEC America LLC 2012...

  • Page 85: Power Signal Mapping

    GPIO EB Pin GPIO EB Signal 49C, 50C, 51C, 49D, 50D, 51D VCC4 VCC_3V3 52C, 53C, 54C, 52C, 53D, 54D VCC3 55C, 56C, 57C, 55D, 56D, 57D VCC2 VCC_5V0 58C, 59C, 60C, 58D, 59D, 60D VCC1 © PHYTEC America LLC 2012...

  • Page 86: Revision History

    L-783e_0 Revision History Table 32-1. Revision History Date Version Number Changes in this Manual 12/11/12 L-783e_0 Preliminary release © PHYTEC America LLC 2012...