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The TVP5154A video decoder has an internal vertical data processor (VDP) that can be used to slice
various VBI data services such as V-Chip, Teletext (WST, NABTS), closed captioning (CC), wide screen
signaling (WSS), copy generation management system (CGMS), video program system (VPS), electronic
program guide (EPG or Gemstar), program delivery control (PDC) and vertical interval time code (VITC).
This application report provides an introduction to the VBI data slicing capabilities of the TVP5154A and
focuses on configuring the TVP5154A for the more commonly used VBI data services.
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Copyright © 2010, Texas Instruments Incorporated
TVP5154A VBI Quick Start
ABSTRACT
Contents
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List of Figures
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List of Tables
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Application Report
SLEA104 - July 2010
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TVP5154A VBI Quick Start
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Summary of Contents for Texas Instruments TVP5154A

  • Page 1: Table Of Contents

    ..............................ABSTRACT The TVP5154A video decoder has an internal vertical data processor (VDP) that can be used to slice various VBI data services such as V-Chip, Teletext (WST, NABTS), closed captioning (CC), wide screen signaling (WSS), copy generation management system (CGMS), video program system (VPS), electronic program guide (EPG or Gemstar), program delivery control (PDC) and vertical interval time code (VITC).
  • Page 2: Introduction

    Note: This document will focus primarily on the more commonly used dedicated I C data registers. Prior to accessing the VBI sliced data, the TVP5154A must be configured for the desired VBI data service. This includes loading of the VDP Configuration RAM (C-RAM) and the Line Mode registers that are used to enable various data services.
  • Page 3: The Vdp Configuration Ram Is Loaded Prior To Line Mode Register Setup

    Introduction www.ti.com Figure 1. The VDP Configuration RAM is Loaded Prior to Line Mode Register Setup SLEA104 – July 2010 TVP5154A VBI Quick Start Copyright © 2010, Texas Instruments Incorporated...
  • Page 4: Vdp Configuration Ram

    VDP Configuration RAM The first step in configuring the TVP5154A for VBI data slicing is to load the VDP Configuration RAM (C-RAM). The C-RAM defines the data slicing modes for the various data services, with each mode having its own unique RAM address and 16 byte block of memory.
  • Page 5: Line Mode Registers

    FIFO routing are also available in the line mode registers. Unused line mode and line address registers must be programmed with FFh. A detailed description of these registers is shown in Appendix A. The TVP5154A VDP is based on an NTSC line numbering convention, resulting in a 3-line VDP offset SLEA104 – July 2010 TVP5154A VBI Quick Start Copyright ©...
  • Page 6: Line Mode Setup For Wss/Cgms

    // line 26 field 2 (0xF9), mode bits = 0x08 I2CWriteByte(TVP5154A, 0xCB, 0x4E); // Set Pixel Alignment [7:0]to 0x4E I2CWriteByte(TVP5154A, 0xCC, 0x00); // Set Pixel Alignment [9:8]to 0x00 Figure 3. Line Mode Setup for WSS/CGMS TVP5154A VBI Quick Start SLEA104 – July 2010 Copyright © 2010, Texas Instruments Incorporated...
  • Page 7: Sliced Data Retrieval

    Sliced Data Retrieval www.ti.com Sliced Data Retrieval The TVP5154A provides dedicated I C registers (see Table 4) for the retrieval of sliced data. Due to higher bandwidth requirements, teletext data is stored in a 512-byte FIFO. With all other data services, sliced data can be automatically sent to the dedicated registers or to the FIFO depending on the line mode setup.
  • Page 8: Fifo Access

    FIFO. A VDP FIFO Interrupt threshold register (C8h), FIFO word count register (C7h), and FIFO full/empty status bits (C6h) are available for managing FIFO data flow. TVP5154A VBI Quick Start SLEA104 – July 2010 Copyright © 2010, Texas Instruments Incorporated...
  • Page 9: Ancillary Data

    Fill byte makes a multiple of 4 bytes from byte zero to last fill byte. Note: The number of bytes (m) varies depending on the VBI data service. SLEA104 – July 2010 TVP5154A VBI Quick Start Copyright © 2010, Texas Instruments Incorporated...
  • Page 10: Full-Field Mode

    VBI Raw Data Mode The TVP5154A offers a VBI raw data mode for use in systems where VBI data slicing and processing is handled in the digital backend receiver instead of the video decoder. In this mode of operation, the decoders are configured to output raw 2x over-sampled luma data on the ITU-R BT.656 output during the...
  • Page 11: Line 21 Closed Caption Itu-R Bt.656 Digital Output Capture With Yuv Samples Present Raw Data Mode Disabled

    Figure 6. Line 21 Closed Caption ITU-R BT.656 Digital Output Capture in Raw Data Mode UV (chroma) data are replaced with Y (luma) data Note: The full-scale transitions are embedded sync codes. SLEA104 – July 2010 TVP5154A VBI Quick Start Copyright © 2010, Texas Instruments Incorporated...
  • Page 12: Appendix A Subset Of The Tvp5154A Vdp I C Registers

    Appendix A Subset of the TVP5154A VDP I C Registers VDP Closed Caption Data Address 90h-93h Read only Address Closed Caption Field 1 byte 1 Closed Caption Field 1 byte 2 Closed Caption Field 2 byte 1 Closed Caption Field 2 byte 2 These registers contain the closed caption data arranged in bytes per field.
  • Page 13 VITC Seconds byte 2 VITC Minutes byte 1 VITC Minutes byte 2 VITC Hours byte 1 VITC Hours byte 2 VITC CRC byte These registers contain the VITC data. SLEA104 – July 2010 TVP5154A VBI Quick Start Copyright © 2010, Texas Instruments Incorporated...
  • Page 14 RAM for only those standards of interest. Registers D0h-FBh must all be programmed with FFh, before writing or reading the configuration RAM. Full field mode (CFh) must be disabled as well. TVP5154A VBI Quick Start SLEA104 – July 2010 Copyright © 2010, Texas Instruments Incorporated...
  • Page 15 This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default 80h). This interrupt must be enabled at address C1h. 1 word equals 2 bytes. SLEA104 – July 2010 TVP5154A VBI Quick Start Copyright © 2010, Texas Instruments Incorporated...
  • Page 16 This register is programmed to allow host port access to the FIFO or allow all VDP data to go out the video port. Output FIFO data to the video output Y[7:0] Allow host port access to the FIFO data (default) TVP5154A VBI Quick Start SLEA104 – July 2010 Copyright © 2010, Texas Instruments Incorporated...
  • Page 17 FFh are sliced with the definition of register FCh. Values other than FFh in the line-mode registers allow a different slice mode for that particular line. SLEA104 – July 2010 TVP5154A VBI Quick Start Copyright © 2010, Texas Instruments Incorporated...
  • Page 18 Line 24 Field 2 Line 25 Field 1 Line 25 Field 2 Line 26 Field 1 Line 26 Field 2 Line 27 Field 1 Line 27 Field 2 TVP5154A VBI Quick Start SLEA104 – July 2010 Copyright © 2010, Texas Instruments Incorporated...
  • Page 19 This allows each VBI line to be programmed independently but have the remaining lines in full-field mode. The full-field mode register has the same bits definition as line-mode registers. (default 7Fh) SLEA104 – July 2010 TVP5154A VBI Quick Start Copyright © 2010, Texas Instruments Incorporated...
  • Page 20: Appendix B Sample Winvcc Cmd File For Vbi Setup

    // Enable FIFO access, disable ANC data WR_REG,VID_DEC,0x01,0xCB,0x4E // Set Pixel Alignment [7:0] to 4Eh WR_REG,VID_DEC,0x01,0xCC,0x00 // Set pixel Alignment [9:8] to 0 END_DATASET ///////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////// TVP5154A VBI Quick Start SLEA104 – July 2010 Copyright © 2010, Texas Instruments Incorporated...
  • Page 21: Appendix C Example Tvp5154A C Code

    Appendix C Example TVP5154A C Code // TVP5154A WSS/CGMS Example #define TVP5154A 0xB8; // TVP5154A main I2C address byte I2C_RegAddress,Status; byte I2C_Data; int CRAM_Address, count; // recommended WSS/CGMS settings byte WSS_ARRAY[]={0x38,0,0x3F,0,0,0x71,0x6E,0x43,0x63,0x7C,0x08,0,0,0,0x39,0}; byte WSSData[3]; // data array for WSS/CGMS ////////////////////////////////////////////////////////////////////////////////...
  • Page 22: Appendix Dvbi Raw Data I 2 C Registers

    GPCL/VBLK signal when it is configured to output vertical blank. The setting in this register also determines the duration of the luma bypass function (see register 07h). TVP5154A VBI Quick Start SLEA104 – July 2010 Copyright © 2010, Texas Instruments Incorporated...
  • Page 23 GPCL/VBLK signal when it is configured to output vertical blank (see register 03h). The setting in this register also determines the duration of the luma bypass function (see register 07h). SLEA104 – July 2010 TVP5154A VBI Quick Start Copyright © 2010, Texas Instruments Incorporated...
  • Page 24 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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