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10-Bit Resolution, 30 MSPS
Analog-to-Digital Converter
Configurable Input Functions:
– Single-Ended
– Single-Ended With Analog Clamp
– Single-Ended With Programmable Digital
Clamp
– Differential
Built-In Programmable Gain Amplifier
(PGA)
Differential Nonlinearity: ± 0.3 LSB
Signal-to-Noise: 56 dB
Spurious Free Dynamic Range: 60 dB
Adjustable Internal Voltage Reference
Straight Binary/2s Complement Output
Out-of-Range Indicator
Power-Down Mode
description
The THS1031 is a CMOS, low-power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with
a supply range from 3 V to 5.5 V. The THS1031 has been designed to give circuit developers flexibility. The
analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp amplifier
whose clamp input level can be driven from an external dc source or from an internal high-precision 10-bit digital
clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR for small
signals. The THS1031 provides a wide selection of voltage references to match the user's design requirements.
For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the application. The out-of-range output indicates any
out-of-range condition in THS1031's input signal. The format of digital output can be coded in either unsigned
binary or 2s complement.
The speed, resolution, and single-supply operation of the THS1031 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function
allows dc restoration of video signal and is suitable for video applications. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both
imaging and communications systems.
The THS1031C is characterized for operation from 0°C to 70°C, while the THS1031I is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
AVAILABLE OPTIONS
PACKAGED DEVICES
T A
T A
28-TSSOP (PW)
0°C to 70°C
THS1031CPW
– 40°C to 85°C
THS1031IPW
•
POST OFFICE BOX 655303
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
28-PIN TSSOP/SOIC PACKAGE
(TOP VIEW)
AGND
1
DV
2
DD
I/O0
3
I/O1
4
I/O2
5
I/O3
6
I/O4
7
I/O5
8
I/O6
9
I/O7
10
I/O8
11
I/O9
12
OVR
13
DGND
14
28-SOIC (DW)
THS1031CDW
THS1031IDW
Copyright 2002, Texas Instruments Incorporated
DALLAS, TEXAS 75265
THS1031
AV
28
DD
AIN
27
VREF
26
REFBS
25
REFBF
24
MODE
23
REFTF
22
REFTS
21
CLAMPIN
20
CLAMP
19
REFSENSE
18
WR
17
OE
16
CLK
15
1
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Related Manuals for Texas Instruments THS1031
Summary of Contents for Texas Instruments THS1031
- Page 1 The THS1031 is a CMOS, low-power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with a supply range from 3 V to 5.5 V. The THS1031 has been designed to give circuit developers flexibility. The analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp amplifier whose clamp input level can be driven from an external dc source or from an internal high-precision 10-bit digital clamp level programmable via an internal CLAMP register.
-
Page 2: Functional Block Diagram
THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 functional block diagram Power Down 10-Bit Clamp Control CLAMPIN Register CLAMP Clamp Amplifier Core Sample Output I/O(0–9) REFTS Buffer Hold REFBS Internal... - Page 3 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 Terminal Functions TERMINAL DESCRIPTION DESCRIPTION NAME AGND Analog ground Analog input AV DD Analog supply CLAMP High to enable clamp mode, low to disable clamp mode CLAMPIN Connect to an external analog clamp reference input.
- Page 4 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 † absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range: AV to AGND, DV to DGND .......
- Page 5 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 electrical characteristics over recommended operating conditions, AV = 3 V, DV = 3 V, = 30 MSPS/50% duty cycle, MODE = AV , 2-V input span from 0.5 V to 2.5 V, external reference,...
- Page 6 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 electrical characteristics over recommended operating conditions, AV = 3 V, DV = 3 V, = 30 MSPS/50% duty cycle, MODE = AV , 2-V input span from 0.5 V to 2.5 V, external reference,...
- Page 7 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 electrical characteristics over recommended operating conditions, AV = 3 V, DV = 3 V, = 30 MSPS/50% duty cycle, MODE = AV , 2-V input span from 0.5 V to 2.5 V, external reference,...
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Page 8: Parameter Measurement Information
THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PARAMETER MEASUREMENT INFORMATION See Note A t w(WP) t d(WOE) t d(OEW) t d(DZ) t su t d(DEN) Hi-Z Hi-Z Output Input Output NOTE A: All timing measurements are based on 50% of edge transition. -
Page 9: Typical Characteristics
THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 TYPICAL CHARACTERISTICS POWER DISSIPATION SAMPLING FREQUENCY AV DD = DV DD = 3 V f i = 3.5 MHz T A = 25°C f s –... - Page 10 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS SAMPLING FREQUENCY 10.0 AV DD = DV DD = 3 V f i = 3.5 MHz T A = 25°C...
- Page 11 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS SAMPLING FREQUENCY 10.00 9.50 9.00 8.50 8.00 AV DD = DV DD = 5 V, f i = 3.5 MHz 7.50...
- Page 12 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY INPUT CODE AV DD = 3 V DV DD = 3 V f s = 30 MSPS –0.5 –1.0...
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Page 13: Principles Of Operation
REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user. The THS1031 offers a clamp function for dc restoration of ac-coupled signals. The clamp voltage may be set digitally via the 10-bit clamp DAC or by the analog level applied to the CLAMPIN input. - Page 14 The analog input signal A is applied to the AIN pin, either dc-coupled, ac-coupled, or ac-coupled with dc restoration using the THS1031 clamp circuit. The differential sample and hold processes A with respect to the voltages applied to the REFTS and REFBS pins, to give a differential output VP+ –...
- Page 15 ADC reference generation The THS1031 has three primary modes of ADC reference generation, selected by the voltage level applied to the MODE pin. Connecting the MODE pin to AGND gives full external reference mode. In this mode, the user supplies the ADC reference voltages directly to pins REFTF and REFBF.
- Page 16 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION full external reference mode (mode = AGND) REFTF AIN+ Sample Core REFTS –1/2 Hold –1/2 REFBS REFBF Internal Reference Buffer Figure 12.
- Page 17 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION full external reference mode (mode = AGND) (continued) AV DD AV DD REFSENSE –FS REFTS REFBS AV DD REFTF GAIN + [(FS+) –...
- Page 18 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION differential mode (mode = AV /2) (continued) AV DD AIN+ MODE –FS REFTS AIN– –FS REFBS REFSENSE 0.1 µF...
- Page 19 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION top/bottom mode (MODE = AV REFTF = AV DD + (REFTS – REFBS) AIN+ Sample Core REFTS –1/2 Hold –1/2...
- Page 20 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION onboard reference generator configuration The onboard reference generator (ORG) can supply a supply-voltage-independent and temperature- independent voltage on pin VREF.
- Page 21 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION onboard reference generator configuration (continued) Internal Reference Buffer Mode = AV DD VREF = 2 V 0.1 µF 1 µF 10 kΩ...
- Page 22 Figure 24 shows the operating configuration in top/bottom mode for a 2-V span single-ended input, using VREF to drive REFTS and with PGA gain = 1. Connecting the MODE pin to AV puts the THS1031 in top/bottom mode. Connecting pin REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are user-connected to VREF and AGND respectively to match the AIN pin input range to the voltage range of the input signal.
- Page 23 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION operating configuration examples (continued) In Figure 25, the input signal is differential, so Mode = AV /2 (differential mode) is set to allow the inverse signal to be applied to REFTS and REFBS.
- Page 24 V IN Figure 28. Schematic of Clamp Circuitry The THS1031 provides a clamp function for restoring a dc reference level to the signal at AIN which has been lost through ac-coupling from the signal source to this pin. Figure 29 shows an example of using the clamp to restore the black level of a composite video input ac coupled to AIN.
- Page 25 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION clamp operation (continued) Line Sync Black Level Video at AIN CLAMP Figure 29. Example Waveforms for Line-Clamping to a Video Input Black Level...
- Page 26 1 mW of power in either top/bottom or center-span modes. Power-down mode is exited by resetting control register bit 3 to 0. On power up, the THS1031 typically requires 5 ms of wake-up time before valid conversion results are available.
- Page 27 The THS1031 contains two clamp registers and a control register for user programming of THS1031 operation. Binary data can be written into these registers by using pins I/O0 to I/O9 and the WR and OE pins (see the previous section).
- Page 28 THS1301 analog inputs driving AIN Figure 32 shows an equivalent circuit for the THS1031 AIN pin. The load presented to the system at the AIN pin comprises the switched input sampling capacitor, C , and various stray capacitances, C...
- Page 29 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION AIN input current and input load modeling (continued) R< 20 Ω Figure 33. Damping Source Ringing Using a Small Resistor equivalent input resistance at AIN and ac-coupling to AIN Some applications may require ac-coupling of the input signal to the AIN pin.
- Page 30 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION details The above value for R is derived by noting that the average AIN voltage must equal the bias voltage supplied by the ac coupling network.
- Page 31 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION driving the internal reference buffer (top/bottom mode) Figure 36 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal reference buffer only.
- Page 32 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION driving REFTF and REFBF (full external reference mode) AV DD REFTF To REFBS (For Kelvin Connection) AGND 680 Ω...
- Page 33 For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of 1.3 V at the THS1031 input. The voltage Vc required across the input coupling capacitor is thus 1.3 – 0.3 = 1 V.
- Page 34 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 PRINCIPLES OF OPERATION clamp operation (continued) Thus if a constant voltage is applied to the clamp input that drives the ADC output to code 1023 (with no...
- Page 35 The THS1031 outputs are capable of driving rail-to-rail with up to 20 pF of load per pin at 30 MHz clock and 3 V digital supply. Minimizing the load on the outputs will improve THS1031 signal-to-noise performance by reducing the switching noise coupling from the THS1031 output buffers to the internal analog circuits.
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Page 36: Mechanical Data
THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE 16 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.010 (0,25) 0.014 (0,35) 0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.010 (0,25) NOM... - Page 37 THS1031 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE 14 PINS SHOWN 0,30 0,10 0,65 0,19 0,15 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–...
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Page 38: Packaging Information
PACKAGE OPTION ADDENDUM www.ti.com 27-Mar-2009 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing THS1031CDW ACTIVE SOIC Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) THS1031CDWG4 ACTIVE SOIC Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) -
Page 39: Tape And Reel Information
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel A0 (mm) B0 (mm) K0 (mm) Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1 (mm) THS1031CPWR TSSOP 2000 330.0 16.4 10.2 12.0... - Page 40 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) THS1031CPWR TSSOP 2000 346.0 346.0 33.0 Pack Materials-Page 2...
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Page 41: Important Notice
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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