Texas Instruments TVP5147M1PFP Data Manual
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Texas Instruments TVP5147M1PFP Data Manual

Ntsc/pal/secam 2x10-bit digital video decoder with macrovision detection, ypbpr inputs, and 5-line comb filter
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TVP5147M1PFP
NTSC/PAL/SECAM 2y10 Bit Digital Video
Decoder With MacrovisionE Detection, YPbPr
Inputs, and 5 Line Comb Filter
Data Manual
March 2007
Digital Audio Video
SLES140A

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Summary of Contents for Texas Instruments TVP5147M1PFP

  • Page 1 TVP5147M1PFP NTSC/PAL/SECAM 2y10 Bit Digital Video Decoder With MacrovisionE Detection, YPbPr Inputs, and 5 Line Comb Filter Data Manual March 2007 Digital Audio Video SLES140A...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

  • Page 3: Table Of Contents

    Section Introduction ................Detailed Functionality .
  • Page 4 Contents Section 2.11.11 Luminance Contrast Register 2.11.12 Chrominance Saturation Register 2.11.13 Chroma Hue Register 2.11.14 Chrominance Processing Control 1 Register 2.11.15 Chrominance Processing Control 2 Register 2.11.16 AVID Start Pixel Register 2.11.17 AVID Stop Pixel Register 2.11.18 HSYNC Start Pixel Register 2.11.19 HSYNC Stop Pixel Register 2.11.20...
  • Page 5 Section 2.11.59 Analog Output Control 1 Register 2.11.60 Chip ID MSB Register 2.11.61 Chip ID LSB Register 2.11.62 CPLL Speed Control Register 2.11.63 Status Request Register 2.11.64 Vertical Line Count Register 2.11.65 AGC Decrement Delay Register 2.11.66 VDP TTX Filter And Mask Registers 2.11.67 VDP TTX Filter Control Register 2.11.68...

  • Page 6: Section Page

    Contents Section Electrical Characteristics 3.3.1 DC Electrical Characteristics 3.3.2 Analog Processing and A/D Converters 3.3.3 Timing ..............Example Register Settings .
  • Page 7 Figure 1−1 Functional Block Diagram ............. 1−2 Terminal Assignments Diagram 2−1...

  • Page 8: List Of Tables

    List of Tables Table 1−1 Terminal Functions ..............2−1 Output Format .

  • Page 9: Introduction

    Macrovision copy protection detection circuit (Type 1, 2, 3, and separate color stripe detection) • 3.3-V tolerant digital I/O ports Macrovision is a trademark of Macrovision Corporation. Other trademarks are the property of their respective owners. SLES140A—March 2007 C host port interface. Furthermore, luma peaking (sharpness) with Introduction TVP5147M1PFP...

  • Page 10: Detailed Functionality

    Single 14.31818-MHz reference crystal for all standards − Line-locked internal pixel sampling clock generation with horizontal and vertical lock signal outputs − Genlock output RTC format for downstream video encoder synchronization • Certified Macrovision copy protection detection TVP5147M1PFP SLES140A—March 2007...

  • Page 11: Tvp5147M1 Applications

    TVP5150AM1 Ultralow Power NTSC/PAL/SECAM Video Decoder With Robust Sync Detector (SLES098) Ordering Information 0°C to 70°C Gemstar is a trademark of Gemstar-TV Guide Intermational. PowerPAD is a trademark of Texas Instruments. SLES140A—March 2007 PACKAGED DEVICES 80-TERMINAL PLASTIC FLAT-PACK PowerPADE PACKAGE...

  • Page 12: Functional Block Diagram

    VI_2_B VI_2_C 2 × 11-Bit VI_3_A CVBS/ VI_3_B C/Pr VI_3_C CVBS/Y VI_4_A Sampling Clock With Sync Detector Figure 1−1. Functional Block Diagram TVP5147M1PFP CVBS/Y Data Processor Composite and S-Video Processor Luma CVBS/Y Separation Processing 5-line Chroma C/CbCr Adaptive Processing Comb...

  • Page 13: Terminal Assignments

    72 71 70 69 68 67 66 65 64 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Introduction 63 62 61 C_6/GPIO C_7/GPIO C_8/GPIO C_9/GPIO DGND DVDD IOGND IOVDD DGND DVDD TVP5147M1PFP...

  • Page 14: Terminal Functions

    Power down input: PWDN 1 = Power down 0 = Normal mode RESETB Reset input, active low (see Section 2.8) Host Interface I 2 C clock input I 2 C data bus TVP5147M1PFP Table 1−1. Terminal Functions DESCRIPTION DESCRIPTION SLES140A—March 2007...
  • Page 15 Vertical sync output (for modes with dedicated VSYNC) or VBLK output VS/VBLK/GPIO Programmable general-purpose I/O Odd/even field indicator output. This terminal needs a pulldown resistor (see Figure 5−1). FID/GPIO Programmable general-purpose I/O Active video indicator output AVID/GPIO Programmable general-purpose I/O SLES140A—March 2007 DESCRIPTION DESCRIPTION TVP5147M1PFP Introduction...
  • Page 16 Introduction TVP5147M1PFP SLES140A—March 2007...

  • Page 17: Functional Description

    I input configurations, some of which are: SLES140A—March 2007 Analog Front End C interface. The 10 analog video inputs can be used for different Functional Description CH1 A/D 11-Bit CH2 A/D 11-Bit Line-Locked Sampling Clock TVP5147M1PFP...

  • Page 18: Analog Input Clamping

    All ADCs have a resolution of 10 bits and can operate up to 30 MSPS. All A/D channels receive an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and 30 MHz. All ADC reference voltages are generated internally. TVP5147M1PFP C subaddress 00h (see Section 2.11.1). to 2.0-V to a full-scale 10-bit A/D output code .

  • Page 19: Digital Video Processing

    Contrast, brightness, sharpness, hue, and saturation controls are programmable through the host port. SLES140A—March 2007 VBI Data Slice VBI Data Processor CVBS/Y Composite C/CbCr Processor VS/VBLK Timing HS/CS Processor GLCO AVID Functional Description Y[9:0] Output Formatter C[9:0] YCbCr Host Interface TVP5147M1PFP...

  • Page 20: Composite And S-Video Processing Block Diagram

    U and V side bands, it is desirable to limit the filter bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the three notch filters. Figure 2−4 and Figure 2−5 represent the frequency responses of the wideband color low-pass filters. TVP5147M1PFP Peaking – NTSC/PAL...

  • Page 21: Color Low-Pass Filter With Filter Characteristics, Ntsc/Pal Itu-R Bt.601 Sampling

    −3 dB @ 844 kHz Filter 0 −3 dB @ 1.41 MHz Filter 3 −3 dB @ 554 kHz Filter 1 −3 dB @ 1.03 MHz f − Frequency − MHz Sampling Notch 3 Filter f − Frequency − MHz TVP5147M1PFP...

  • Page 22: Luminance Processing

    −1 2.2.4 Color Transient Improvement Color transient improvement (CTI) enhances horizontal color transients. The color difference signal transition points are maintained, but the edges are enhanced for signals which have bandwidth-limited color components. TVP5147M1PFP C interface. Gain Bandpass × Filter Peak at f = 2.64 MHz...

  • Page 23: Clock Circuits

    23-bit PLL frequency control word, and F ctrl Valid Sample Reserved 18 CLK 45 CLK 23-Bit Fsc PLL Increment 1 CLK Figure 2−11. RTC Timing Functional Description 14.318-MHz Crystal C L1 C L2 sclk Invalid Sample 3 CLK TVP5147M1PFP...

  • Page 24: Separate Syncs

    The default settings for 525-line and 625-line video outputs are given as examples below. FID changes at the same transient time when the trailing edge of vertical sync occurs. The polarity of FID is programmable by an I TVP5147M1PFP Table 2−1. Output Format TERMINAL...

  • Page 25: Vertical Synchronization Signals For 525-Line System

    VBLK Start Second Field Video VBLK VBLK Start NOTE: Line numbering conforms to ITU-R BT.470 Figure 2−12. Vertical Synchronization Signals for 525-Line System SLES140A—March 2007 525-Line VS Start VS Stop VS Start VS Stop Functional Description VBLK Stop VBLK Stop TVP5147M1PFP...

  • Page 26: Vertical Synchronization Signals For 625-Line System

    First Field Video VBLK VBLK Start Second Field Video VBLK VBLK Start NOTE: Line numbering conforms to ITU-R BT.470 Figure 2−13. Vertical Synchronization Signals for 625-Line System TVP5147M1PFP 625-Line VS Start VS Stop VS Start VS Stop VBLK Stop VBLK Stop...

  • Page 27: Horizontal Synchronization Signals For 10-Bit 4:2:2 Mode

    NOTE: ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference Figure 2−14. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode SLES140A—March 2007 Horizontal Blanking HS Start HS Stop DATACLK = 2× Pixel Clock Mode NTSC 601 PAL 601 Functional Description AVID Start TVP5147M1PFP...

  • Page 28: Horizontal Synchronization Signals For 20-Bit 4:2:2 Mode

    AVID AVID Stop NOTE: AVID rising edge occurs 4 clock cycles early. NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference Figure 2−15. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode TVP5147M1PFP Horizontal Blanking Horizontal Blanking HS Start HS Stop DATACLK = 1× Pixel Clock...

  • Page 29: Embedded Syncs

    I SLES140A—March 2007 H/2 + B/2 20-Bit (PCLK = 1× Pixel Clock) Table 2−3. EAV and SAV Sequence C host interface. The I C device address. Functional Description H/2 + B/2 C standard consists of two C bus, TVP5147M1PFP...

  • Page 30: Reset And I C Bus Address Selection

    C bus address = Example shown that I 2.6.3 VBUS Access The TVP5147M1 decoder has additional internal registers accessible through an indirect access to an internal 24-bit address wide VBUS. Figure 2−17 shows the VBUS register access. TVP5147M1PFP C Host Interface Terminal Description TYPE DESCRIPTION...

  • Page 31: Vbus Access

    ACK P Read Data Figure 2−17. VBUS Access Functional Description 00 0000h 80 051Ch 80 0520h 80 052Ch VITC 80 0600h Line Mode 80 0700h 90 1904h FIFO FF FFFFh ACK P • • • Read Data NAK P TVP5147M1PFP...

  • Page 32: Vbi Data Processor

    Closed Caption WSS-CGMS VITC VITC VPS (PDC) V-Chip (decoded) Gemstar 1x Gemstar 2x User TVP5147M1PFP Table 2−6. Supported VBI System STANDARD LINE NUMBER SECAM 6−23 (Fields 1 and 2) 6−22 (Fields 1 and 2) NTSC 10−21 (Fields 1 and 2) NTSC-J 10−21 (Fields 1 and 2)

  • Page 33: Vbi Fifo And Ancillary Data In Video Stream

    Secondary data ID (SDID) Number of 32-bit data (NN) Internal data ID0 (IDID0) Internal data ID1 (IDID1) 1 st word Data byte word Data byte Data byte Data byte N th word Data byte word Check sum Fill byte TVP5147M1PFP...

  • Page 34: Vbi Raw Data Output

    (3.3 V and 1.8 V) 1 ms (min) RESETB (Pin 34) (Pin 29) The following register writes must be made before normal operation of the device. TVP5147M1PFP 1. Data 2. Data n−5. Data n–4. Data Table 2−9. Reset Sequence DURING RESET...

  • Page 35: Adjusting External Syncs

    R/W = Read and write Reserved register addresses must not be written to. SLES140A—March 2007 Table 2−10. I C Register Summary I 2 C SUBADDRESS 0Fh−15h 16h−17h 18h−19h 1Ah−1Bh 1Ch−1Dh 1Eh−1Fh 20h−21h Functional Description DEFAULT 055h 325h 000h 040h 004h 007h TVP5147M1PFP...
  • Page 36 Reserved AGC white peak processing NOTE: R = Read only W = Write only R/W = Read and write Reserved register addresses must not be written to. TVP5147M1PFP C Register Summary (Continued) I 2 C SUBADDRESS DEFAULT 22h−23h 001h 24h−25h 015h 26h−2Ah...
  • Page 37 W = Write only R/W = Read and write Reserved register addresses must not be written to. SLES140A—March 2007 C Register Summary (Continued) I 2 C SUBADDRESS DEFAULT 7Ah−7Eh 84h−96h 98h−99h 9Ah−9Bh 9Ch−9Dh 9Fh−B0h C2h−C3h 01Eh C4h−D5h DBh−DFh Functional Description TVP5147M1PFP...

  • Page 38: Vbus Register Summary

    Interrupt configuration Reserved NOTE: Writing any value to a reserved register may cause erroneous operation of the TVP5147M1 decoder. It is recommended not to access any data to/from reserved registers. TVP5147M1PFP C Register Summary (Continued) I 2 C SUBADDRESS E3h−E7h E8h−EAh...

  • Page 39: Register Definitions

    Table 2−12 are supported. SLES140A—March 2007 Input select [7:0] INPUT SELECT [7:0] Functional Description OUTPUT OUTPUT (see Note 1) VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A VI_2_B(Y) VI_2_C(Y) VI_2_A(Y) VI_2_B(Y) VI_2_C(Y) VI_4_A(Y) VI_4_A(Y) VI_4_A(Y) VI_4_A(Y) VI_4_A(Y) VI_2_B(Y) VI_2_C(Y) TVP5147M1PFP...

  • Page 40: Afe Gain Control Register

    With the autoswitch code running, the user can force the decoder to operate in a particular video standard mode by writing the appropriate value into this register. Changing these bits causes the register settings to be reinitialized. TVP5147M1PFP Video standard [2:0] Component Video...

  • Page 41: Operation Mode Register

    (M, J ) NTSC: 0 = Reserved 1 = Autoswitch includes (M, J) NTSC (default) SLES140A—March 2007 Reserved NTSC 4.43 (Nc) PAL NOTE: Bits 1 and 0 must always be 1. Functional Description Power save (M) PAL (M, J) NTSC TVP5147M1PFP...

  • Page 42: Color Killer Register

    Luminance signal delay [3:0]: Luminance signal delays with respect to the chroma signal in 1× pixel clock increments. 0111 = Reserved 0110 = 6-pixel delay 0001 = 1-pixel delay 0000 = 0 delay (default) 1111 = −1-pixel delay 1000 = −8-pixel delay TVP5147M1PFP Color killer threshold [4:0] VBI raw Luminance signal delay [3:0] SLES140A—March 2007...

  • Page 43: Luminance Processing Control 2 Register

    1111 1111 = 255 (bright) 1000 0000 = 128 (default) 0000 0000 = 0 (dark) SLES140A—March 2007 Reserved Peaking gain [1:0] Reserved PAL ITU-R BT.601 1.2129 1.2129 0.8701 0.8701 0.7183 0.7383 0.5010 0.5010 Brightness [7:0] Functional Description Reserved Trap filter select [1:0] TVP5147M1PFP...

  • Page 44: Chrominance Processing Control 1 Register

    Automatic color gain control (ACGC) [1:0]: 00= ACGC enabled (default) 01 = Reserved 10= ACGC disabled, ACGC set to the nominal value 11= ACGC frozen to the previous set value TVP5147M1PFP Contrast [7:0] Saturation [7:0] Hue [7:0] Chrominance adaptive Reserved...

  • Page 45: Chrominance Processing Control 2 Register

    The AVID start pixel register also controls the position of the SAV code. SLES140A—March 2007 PAL compensation AVID start [7:0] AVID active Reserved NTSC Sqp PAL 601 86 (56h) 88 (58h) Functional Description Chrominance filter select [1:0] AVID start [9:8] PAL Sqp 103 (67h) TVP5147M1PFP...

  • Page 46: Hsync Start Pixel Register

    VSYNC start MSB is written to. If the user changes these registers, then the TVP5147M1 decoder retains values in different modes until this decoder resets. NTSC: default 004h PAL: default 001h TVP5147M1PFP AVID stop [7:0] Reserved NTSC Sqp...

  • Page 47: Vsync Stop Line Register

    000 = 0 delay (default) 111 = −1-pixel delay 100 = −4-pixel delay SLES140A—March 2007 VSYNC stop [7:0] Reserved VBLK start [7:0] Reserved VBLK stop [7:0] Reserved Functional Description VSYNC stop [9:8] VBLK start [9:8] VBLK stop [9:8] CTI delay [2:0] TVP5147M1PFP...

  • Page 48: Sync Control Register

    0 = VS terminal outputs vertical sync (default) 1 = VS terminal outputs vertical blank HS or CS: 0 = HS terminal outputs horizontal sync (default) 1 = HS terminal outputs composite sync TVP5147M1PFP CTI gain [3:0] Polarity FID Polarity VS Polarity HS...

  • Page 49: Output Formatter 1 Register

    1 = Data clocked out on the rising edge of DATACLK Clock enable: 0 = DATACLK outputs are high-impedance (default). 1 = DATACLK outputs are enabled. SLES140A—March 2007 Reserved Data enable Black Screen [1:0] Functional Description Output format [2:0] CLK polarity Clock enable TVP5147M1PFP...

  • Page 50: Output Formatter 3 Register

    FID [1:0]: FID terminal function select 00 = FID is logic 0 output. 01 = FID is logic 1 output. 10 = FID is FID output. 11 = FID is logic input (default). TVP5147M1PFP AVID [1:0] GLCO [1:0] FID [1:0] SLES140A—March 2007...

  • Page 51: Output Formatter 4 Register

    00 = C_0 is logic 0 output. 01 = C_0 is logic 1 output. 10 = Reserved 11 = C_0 is logic input (default). C_x functions are only available in the 10-bit output mode. SLES140A—March 2007 HS/CS [1:0] C_1 [1:0] Functional Description C_0 [1:0] TVP5147M1PFP...

  • Page 52: Output Formatter 5 Register

    00 = C_2 is logic 0 output. 01 = C_2 is logic 1 output. 10 = Reserved 11 = C_2 is logic input (default). C_x functions are only available in the 10-bit output mode. TVP5147M1PFP C_4 [1:0] C_3 [1:0] C_2 [1:0] SLES140A—March 2007...

  • Page 53: Clear Lost Lock Detect Register

    Clear lost lock detect: Clear bit 4 (lost lock detect) in the status 1 register at subaddress 3Ah (see Section 2.11.34) 0 = No effect (default) 1 = Clears bit 4 in the status 1 register SLES140A—March 2007 C_8 [1:0] C_7 [1:0] Reserved Functional Description C_6 [1:0] Clear lost lock detect TVP5147M1PFP...

  • Page 54: Status 1 Register

    1 = Vertical sync is locked. Horizontal sync lock status: 0 = Horizontal sync is not locked. 1 = Horizontal sync is locked. TV/VCR status: 0 = TV 1 = VCR TVP5147M1PFP Lost lock Color subcarrier Vertical sync detect lock status lock status...

  • Page 55: Agc Gain Status Register

    These AGC gain status registers are updated automatically by the TVP5147M1 decoder with AGC on. In manual gain control mode, these register values are not updated by the TVP5147M1 decoder. SLES140A—March 2007 PAL switch polarity Field sequence status Fine gain [7:0] Functional Description Color killed Macrovision detection [2:0] Fine gain [11:8] TVP5147M1PFP...

  • Page 56: Video Standard Status Register

    C_x input status: 0 = Input is a low. 1 = Input is a high. These status bits are only valid when terminals are used as input and its states updated at every line. TVP5147M1PFP Reserved Component video Reserved Component 525...

  • Page 57: Gpio Input 2 Register

    1 = Input is a high. C_x input status: 0 = Input is a low. 1 = Input is a high. These status bits are only valid when terminals are used as input and its states updated at every line. SLES140A—March 2007 Functional Description TVP5147M1PFP...

  • Page 58: Afe Coarse Gain For Ch 1 Register

    1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7 (default) 0001 = 0.6 0000 = 0.5 TVP5147M1PFP Reserved Reserved SLES140A—March 2007...

  • Page 59: Afe Coarse Gain For Ch 3 Register

    1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7 (default) 0001 = 0.6 0000 = 0.5 SLES140A—March 2007 Reserved Reserved Functional Description TVP5147M1PFP...

  • Page 60: Afe Fine Gain For Y_Chroma Register

    1100 0000 0000 = 1.5 1001 0000 0000 = 1.125 (default) 1000 0000 0000 = 1 0100 0000 0000 = 0.5 0011 1111 1111 to 0000 0000 0000 = Reserved TVP5147M1PFP FGAIN 1 [7:0] FGAIN 2 [7:0] FGAIN 3 [7:0] FGAIN 1 [11:8]...

  • Page 61: Afe Fine Gain For Cvbs_Luma Register

    0 = 0→1 adapts to field 1, 1→0 adapts to field 1+ field 2 (default) 1 = 0→1 adapts to field 2, 1→0 adapts to field 1+ field 2 (for TVP5147M1 EVM) SLES140A—March 2007 FGAIN 4 [7:0] Functional Description FGAIN 4 [11:8] 656 version FID control TVP5147M1PFP...

  • Page 62: F-Bit And V-Bit Control 1 Register

    Switch = V bit switches high before the F bit transition and low after the F bit transition Switch9 = V bit switches high 1 line prior to F bit transition, then low after 9 lines Reserved = Not used TVP5147M1PFP VPLL Adaptive...

  • Page 63: Agc Decrement Speed Control Register

    111 = 7 (slowest) 110 = 6 (default) 000 = 0 (fastest) 2.11.52 ROM Version Register Subaddress Read only ROM Version [7:0]: ROM revision number SLES140A—March 2007 Peak AGC decrement speed [2:0] ROM version [7:0] Functional Description Color Sync TVP5147M1PFP...

  • Page 64: Agc White Peak Processing Register

    If the input sync height is greater than 100% and the AGC-adjusted output video amplitude becomes less than 100%, then the back-end scale factor attempts to increase the contrast in the back end to restore the video amplitude to 100%. TVP5147M1PFP Sync height A Luma peak B...

  • Page 65: F And V Bit Control Register

    Toggles Switch at field boundary ITU−R BT 656 Toggles Switch at field boundary ITU−R BT 656 Pulsed mode Switch at field boundary Reserved Functional Description Phase Det. HPLL V bit ITU−R BT 656 ITU−R BT 656 ITU−R BT 656 TVP5147M1PFP...

  • Page 66: Horizontal Shake Increment Register

    AGC increment delay: Number of frames to delay gain increments 1111 1111 = 255 0001 1110 = 30 (default) 0000 0000 = 0 TVP5147M1PFP Horizontal shake threshold [6:0] Horizontal shake increment [7:0] AGC increment delay [7:0] AGC increment speed [3:0]...

  • Page 67: Analog Output Control 1 Register

    Speed [3:0]: Color PLL speed control 1001 = Faster (default) 1010 = 1011 = Slower Other = Reserved SLES140A—March 2007 AGC enable Chip ID MSB [7:0] Chip ID LSB [7:0] Functional Description Input select Analog Output enable Speed [3:0] TVP5147M1PFP...

  • Page 68: Vertical Line Count Register

    Subaddress Default AGC decrement delay [7:0]: Number of frames to delay gain decrements 1111 1111 = 255 0001 1110 = 30 (default) 0000 0000 = 0 TVP5147M1PFP Reserved Vertical line [7:0] Reserved AGC decrement delay [7:0] Capture Vertical line [9:8]...

  • Page 69: Vdp Ttx Filter And Mask Registers

    Filter 2 pattern 1 Filter 2 pattern 2 Filter 2 pattern 3 Filter 2 pattern 4 Filter 2 pattern 5 Bit 2 Bit 1 Bit 0 H[1] D[0] H[0] Bit 2 Bit 1 Bit 0 H[1] M[0] H[0] H[5] R[1] H[4] TVP5147M1PFP...

  • Page 70: Vdp Ttx Filter Control Register

    TTX filter 1 enable: provides for enabling the teletext filter function within the VDP. 0 = Disabled (default) 1 = Enabled If the filter matches or if the filter mask is all 0s, then a true result is returned. TVP5147M1PFP Filter logic [1:0] Mode TTX filter 2 enable TTX filter 1 enable SLES140A—March 2007...

  • Page 71: Vdp Fifo Word Count Register

    FIFO word count [7:0]: This register provides the number of words in the FIFO. SLES140A—March 2007 PASS 1 Filter 1 Enable PASS 2 Filter 2 Enable Figure 2−19. Teletext Filter Function FIFO word count [7:0] NOTE: 1 word equals 2 bytes. Functional Description PASS Filter Logic TVP5147M1PFP...

  • Page 72: Vdp Fifo Interrupt Threshold Register

    This register is programmed to trigger an interrupt when the video line number exceeds this value in bits [5:0]. This interrupt must be enabled at address F4h. NOTE: The line number value of 0 or 1 is invalid and does not generate an interrupt. TVP5147M1PFP Threshold [7:0] NOTE: 1 word equals 2 bytes.

  • Page 73: Vdp Pixel Alignment Register

    Global line mode register has the same bit definition as the general line mode registers. General line mode has priority over the global line mode. SLES140A—March 2007 Pixel alignment [7:0] Reserved VDP line start [7:0] VDP line stop [7:0] Global line mode [7:0] Functional Description Pixel alignment [9:8] TVP5147M1PFP...

  • Page 74: Vbus Data Access With No Vbus Address Increment Register

    2.11.80 VBUS Data Access With VBUS Address Increment Register Subaddress Default VBUS data [7:0]: VBUS data register for VBUS multibyte read/write transaction. VBUS address is autoincremented after each data byte read/write. TVP5147M1PFP Reserved Full field mode [7:0] VBUS data [7:0] VBUS data [7:0] Full field enable SLES140A—March 2007...

  • Page 75: Interrupt Raw Status 0 Register

    CC F2: CC field 2 data available unmasked 0 = Not available 1 = Available SLES140A—March 2007 FIFO read data [7:0] VBUS address [7:0] VBUS address [15:8] VBUS address [23:16] VITC CC F2 Functional Description C interface. All forms CC F1 Line TVP5147M1PFP...

  • Page 76: Interrupt Raw Status 1 Register

    1 = Passed TTX: Teletext data available masked 0 = Not available 1 = Available WSS: WSS data available masked 0 = Not available 1 = Available TVP5147M1PFP H/V lock Macrovision status changed VITC CC F2 Standard changed FIFO full...

  • Page 77: Interrupt Status 1 Register

    0 = FIFO not full 1 = FIFO was full during write to FIFO, see the interrupt mask 1 register at subaddress F5h for details (see Section 2.11.88) SLES140A—March 2007 H/V lock Macrovision status changed Functional Description Standard changed FIFO full TVP5147M1PFP...

  • Page 78: Interrupt Mask 0 Register

    The host interrupt mask 0 and 1 registers can be used by the external processor to mask unnecessary interrupt sources for the interrupt status 0 and 1 register bits, and for the external interrupt terminal. The external interrupt is generated from all nonmasked interrupt flags. TVP5147M1PFP VITC CC F2...

  • Page 79: Interrupt Clear 0 Register

    0 = Disabled (default) 1 = Clear bit 1 (CC field 1 available) in the interrupt status 0 register at subaddress F2h SLES140A—March 2007 H/V lock Macrovision status changed VITC Functional Description Standard changed FIFO full CC F2 CC F1 Line TVP5147M1PFP...

  • Page 80: Interrupt Clear 1 Register

    0 = No effect (default) 1 = Clear bit 0 (FIFO full flag) in the interrupt status 1 register at subaddress F3h and the interrupt raw status 1 register at subaddress F1h TVP5147M1PFP H/V lock Macrovision status changed Standard changed FIFO full SLES140A—March 2007...

  • Page 81: Vdp Closed Caption Data Register

    WSS field 1 byte 3 WSS field 2 byte 1 WSS field 2 byte 2 WSS field 2 byte 3 Byte WSS field 1 byte 1 WSS field 1 byte 2 WSS field 2 byte 1 WSS field 2 byte 2 TVP5147M1PFP...

  • Page 82: Vdp V-Chip Tv Rating Block 1 Register

    14-V: When incoming video program is TV-14-V rated then this bit is set high PG-V: When incoming video program is TV-PG-S rated then this bit is set high Y7-FV: When incoming video program is TV-Y7-FV rated then this bit is set high TVP5147M1PFP VITC frame byte 1 VITC frame byte 2...

  • Page 83: Vdp V-Chip Tv Rating Block 3 Register

    G: When incoming video program is G rated in MPAA rating then this bit is set high N/A: When incoming video program is N/A rated in MPAA rating then this bit is set high SLES140A—March 2007 TV-PG TV-G TV-Y7 PG-13 Functional Description TV-Y None TVP5147M1PFP...

  • Page 84: Vdp General Line Mode And Line Address Register

    011 = VITC 100 = VPS/PDC (PAL only), Gemstar (NTSC only) 101 = USER 1 110 = USER 2 111 = Reserved (active video) (default) TVP5147M1PFP Line address 1 Line mode 1 Line address 2 Line mode 2 Line address 3...

  • Page 85: Vdp Vps/Gemstar Data Register

    VPS byte 9 VPS byte 10 VPS byte 11 VPS byte 12 VPS byte 13 Gemstar frame code Gemstar byte 1 Gemstar byte 2 Gemstar byte 3 Gemstar byte 4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Functional Description TVP5147M1PFP...

  • Page 86: Interrupt Configuration Register

    0100 = 4.42 0101 = 4.68 0110 = 4.94 0111 = 5.20 2.12.11 Interrupt Configuration Register Subaddress B0 0060h Default Reserved Polarity: Interrupt terminal polarity 0 = Active high (default) 1 = Active low TVP5147M1PFP Gain [3:0] Polarity Reserved SLES140A—March 2007...

  • Page 87: Recommended Operating Conditions

    −0.2 V to 2 V −0.5 V to 4.5 V −0.5 V to 4.5 V −0.2 V to 2 V 0°C to 70°C −65°C to 150°C UNIT 1.65 1.95 1.65 1.95 0.7 IOV DD 0.3 IOV DD −4 °C UNIT 14.31818 ±50 TVP5147M1PFP...

  • Page 88: Electrical Characteristics

    Noise spectrum Differential phase Differential gain Output voltage NOTE 1: Component inputs only TVP5147M1PFP = 3 V to 3.6 V, DV = 1.65 V to 1.95 V, AV = 0°C to 70°C = 1.8 V, AV = 3.3 V, AV...

  • Page 89: Clocks, Video Data, And Sync Timing

    90% to 10% 10% to 90% Valid Data TEST CONDITIONS Data Change Data Figure 3−2. I C Host Port Timing Electrical Specifications UNIT 18.5 18.5 V OH V OL V OH Valid Data V OL UNIT µs µs µs µs Stop TVP5147M1PFP...
  • Page 90 Electrical Specifications TVP5147M1PFP SLES140A—March 2007...

  • Page 91: Example 1

    10-bit ITU-R BT.656 with discrete sync outputs 4.2.2 Recommended Settings Recommended I C writes: This setup requires additional writes to output the discrete sync 10-bit 4:2:2 data, HS, and VS, and to autoswitch between all video formats mentioned above. SLES140A—March 2007 Example Register Settings TVP5147M1PFP...
  • Page 92 20-bit ITU-R BT.656 with discrete sync outputs 4.3.2 Recommended Settings Recommended I C writes: This setup requires additional writes to output the discrete sync 20-bit 4:2:2 data, HS, and VS, and to autoswitch between all video formats mentioned above. TVP5147M1PFP SLES140A—March 2007...
  • Page 93 C register address 34h = Output formatter 2 register C data 11h = Enables YCbCr output and the clock output C register address 36h = Output formatter 4 register C data AFh = Enables HS and VS sync outputs SLES140A—March 2007 Example Register Settings TVP5147M1PFP...
  • Page 94 Example Register Settings TVP5147M1PFP SLES140A—March 2007...

  • Page 95: Application Information

    I2C Address selection 1−2 Base Addr. 0xBA 2−3 Base Addr. 0xB8 Application Information IOVDD3.3V DVDD1.8V 0.1 µF (2) DGND DVDD 0.1 µF IOGND IOVDD 0.1 µF DGND DVDD 0.1 µF 2.2 kΩ (2) DATACLK 0.1 µF GLCO/I2CA AVID RESETB PWDN INTREQ TVP5147M1PFP...
  • Page 96 While the thermal land can be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low-impedance ground plane for the device. More information can be obtained from the TI application note PHY Layout (SLLA020). PowerPAD is a trademark of Texas Instruments. TVP5147M1PFP SLES140A—March 2007...

  • Page 97: Packaging Information

    PACKAGING INFORMATION Orderable Device Status TVP5147M1PFP ACTIVE TVP5147M1PFPG4 ACTIVE TVP5147M1PFPR ACTIVE TVP5147M1PFPRG4 ACTIVE The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

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