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Super X11DPG-HGX2 User's Manual
DCPMM Memory Population Table for 2nd Gen Intel Xeon Scalable-SP
Processors
Modes
P1-DIMMF1
P1-DIMMF2
P1-DIMME1
AD
DRAM1
DCPMM
DRAM1
MM
DRAM1
DCPMM
DRAM1
AD + MM
DRAM3
DCPMM
DRAM3
AD
DRAM1
-
DRAM1
MM
DRAM2
-
DRAM2
AD + MM
DRAM3
-
DRAM3
AD
DRAM1
-
DRAM1
MM
DRAM1
-
DRAM1
AD + MM
DRAM3
-
DRAM3
AD
DCPMM
-
DRAM1
MM
DCPMM
-
DRAM1
AD + MM
-
DRAM3
DCPMM
AD
DCPMM
-
DRAM1
Modes
P1-DIMMF1
P1-DIMMF2
P1-DIMME1
AD
DRAM1
-
DRAM1
AD*
DRAM1
-
DRAM1
DRAM1
DRAM2
DRAM3
Note: DDR4 single rank x8 is not available for DCPMM Memory Mode or App-Direct Mode.
•
* 2nd socket has no DCPMM DIMM
•
Mode definitions: AD=App Direct Mode, MM=Memory Mode, AD+MM=Mixed Mode.
•
For MM, general DDR4+DCPMM ratio is between 1:4 and 1:16. Excessive capacity for DCPMM can be used for AD.
•
For each individual population, rearrangements between channels are allowed as long as the resulting population is
compliant with the PDG rules for 2nd Gen Intel Xeon Scalable-SP (82xx/62xx/52xx/4215 series) processors.
•
For each individual population, please use the same DDR4 DIMM in all slots.
•
For each individual population, sockets are normally symmetric with exceptions for 1 DCPMM per socket and 1 DCPMM
per node case. Currently, DCPMM modules operate at 2666 MHz.
•
No mixing of DCPMM and NVMDIMMs within the same platform is allowed.
•
This DCPMM population guide targets a balanced DCPMM-to-DRAM-cache ratio in MM and MM + AD modes.
DIMM Type
RDIMM
LRDIMM
LRDIMM 3DS
Symmetric Population within 1 CPU Socket
P1-DIMME2
P1-DIMMD1
P1-DIMMD2
DCPMM
DRAM1
DCPMM
DCPMM
DRAM1
DCPMM
DCPMM
DRAM3
DCPMM
-
DRAM1
DCPMM
-
DRAM2
DCPMM
-
DRAM3
DCPMM
DCPMM
DRAM1
DCPMM
DRAM1
DCPMM
DCPMM
DCPMM
DRAM3
DCPMM
-
DRAM1
-
-
DRAM1
-
-
DRAM3
-
DRAM1
DRAM1
DRAM1
Asymmetric Population within 1 CPU Socket
P1-DIMME2
P1-DIMMD1
P1-DIMMD2
-
DRAM1
-
-
DRAM1
-
Legend (for the two tables above)
DDR4 Type
RDIMM
3DS RDIMM
LRDIMM
RDIMM
-
RDIMM
3DS RDIMM
LRDIMM
Legend (for the first two tables above)
DCPMM
Any Capacity (Uniformly for all channels for a given configuration)
Validation Matrix (DDR4 DIMMs Validated w/DCPMM)
Ranks Per DIMM
& Data Width
(Stack)
1Rx4
2Rx8
2Rx4
4Rx4
8Rx4 (4H)
P1-DIMMA2
P1-DIMMA1
P1-DIMMB2
DCPMM
DRAM1
DCPMM
DCPMM
DRAM1
DCPMM
DCPMM
DRAM3
DCPMM
DRAM1
-
DCPMM
DCPMM
DRAM2
-
DCPMM
DRAM3
-
DCPMM
DRAM1
DCPMM
DRAM1
DCPMM
DCPMM
DCPMM
DRAM3
DCPMM
-
DRAM1
-
-
DRAM1
-
-
DRAM3
-
DRAM1
DRAM1
DRAM1
P1-DIMMA2
P1-DIMMA1
P1-DIMMB2
P1-DIMMB1
DCPMM
DRAM1
-
DRAM1
DCPMM
DRAM1
-
DRAM1
Capacity
3DS LRDIMM
Refer to Validation Matrix
-
(DDR4 DIMMs validated with
DCPMM) below.
-
Capacity
DIMM Capacity (GB)
DRAM Density
4Gb
8GB
8GB
16GB
N/A
N/A
36
Channel
P1-DIMMB1
P1-DIMMC2
P1-DIMMC1
Config.
2-2-2
DRAM1
DCPMM
DRAM1
DRAM1
DCPMM
DRAM1
2-2-2
2-2-2
DRAM3
DCPMM
DRAM3
DRAM1
-
DRAM1
2-1-1
DRAM2
-
DRAM2
2-1-1
DRAM3
-
DRAM3
2-1-1
DRAM1
-
DRAM1
2-2-1
DRAM1
-
DRAM1
2-2-1
DRAM3
-
DRAM3
2-2-1
DRAM1
-
DCPMM
1-1-1
1-1-1
DRAM1
-
DCPMM
DRAM3
-
1-1-1
DCPMM
DRAM1
-
DCPMM
2-2-1
Channel
P1-DIMMC2
P1-DIMMC1
Config.
-
DRAM1
2/1-1-1
-
DRAM1
2/1-1-1
8Gb
16GB
16GB
32GB
64GB
128GB
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