Analog Devices EVAL-AD7766 Preliminary Technical Data page 4

EVAL-AD7766/AD7767
There are a further 10 solder link options for various functions. These link options are outlined in Table 2. All solder links are set so that
the user can plug and play the evaluation board direct. The default settings lists the settings for the AD7766/67 evaluation board for
operation with the CED board and are listed in the right hand column of the table.
Table 2.Solder Link Option Functions
Link No. Position Function
SL1 Selects the source of the SCLK applied to the AD7766/67
A Selects CED as SCLK source.
B In stand-alone operation an external SCLK can be applied to the AD7766/67 device by means of J8
SL2 Selects the source of the CS signal to be applied to AD7766/67 device.
A Selects CED as CS source.
B
In stand-alone operation an external CS can be applied to the AD7766/67 device by means of J5
SL3 Selects the source of the signal applied to SDI (serial data input) pin of the AD7766/67, used in daisy-
chain applications.
A Ties SDI pin to 2.5V volts logic high.(default setting for SDI pin when using the AD7766/67 devices
singly.
B Allows user to input data from another AD7766/67 device to verify daisy-chain functionality.
SL4 Selects the path of the DRDY output from the AD7766/67 device
A Use for CED board. Routes the DRDY signal from the AD7766/67 device to the CED control board via
the 96-way connector.
B
In stand-alone operation the DRDY can be routed to the SMB connector J11.
SL5 Selects the MCLK source applied to the AD7766/67 device.
A External MCLK source applied to SMB connector J7 is applied to the AD7766/67 MCLK pin.
B On board crystal oscillator Y1 output is routed to the AD7766/67 applying a 1Mhz clock to the MCLK
pin ( a 1Mhz MCLK signal allows the AD7766/67 devices to operate with an output data rate of 125
kHz, 62.5 kHz, and 31.25 kHz respectively). Placing 1KΩ resistors in postions R43 and R23 allows the
user to potentially divide the 5V output of the crystal to 2.5V as per the V
AD7766/67 evaluation board.
C
Applies the 1.024Mhz MCLK signal created by the CED board to be applied to the AD7766/67 MCLK
pin. Enables the AD7766/67 device to operate at the maximum output data rate.
SL6 Routes the Serial Data Output (SDO) to the CED board or the SMB connector J9.
A Routes the SDO signal to J9, the SMB connector marked "SDO" allowing data to be acquired by an
external element in stand-alone mode.
B Routes the SDO signal to the 96-way connector so that data can be acquired by the CED control
board.
SL7 N/A Not applicable, leave the solder link unused.
SL8 Selects the source of the voltage applied to the V
A A 2.5V supply created by the CED board is supplied to the AD7766/67 V
B Allows the user to apply an external V
C Applies the 2.5V supply created by the ADP3330-2.5 regulator (U11) to the AD7766/67 V
D Allows a 2.5V supply to be applied to the AD7766/67 VDRIVE pin from a star point at the output of the
ADP3330-2.5 regulator (U8) which creates the 2.5V supply for the DVDD pin. When using this option,
ensure that the resistive link between AD7766/67 side of R7 and the D pad of SL8 is shorted.
SL9 Selects the 2.5V path that is routed to the AVDD1 pin of the AD7766/67 device (pin 1).
A Allows the AD7766/67 to be run off one 2.5V regulator by linking the pin to the DVDD star point on
the AD7766/67 side of the resistor R7. Using this option requires that the resistive place holder
between pad A of SL9 and the DVDD star point (device side of R7) is shorted.
B Routes the 2.5V supply created by the ADP3330-2.5 device (U9) to the AVDD1 pin of the AD7766/67
device.
SL11 Selects the source of the common mode voltage (2.5V) applied to the amplifiers (U2 and U3). The
AD7766/67 device must be driven differentially using a common mode of V
divider of 2 x 1KΩ resistors between SL11 and the appropriate pins of the amplifiers. This means that
when using a 5V reference the voltage linked through SL11 should be 5V.
pin.
DRIVE
supply (via the J13 connector) to the AD7766/67 V
DRIVE
Rev. PrA | Page 4 of 20
Preliminary Technical Data
voltage default on the
DRIVE
pin.
DRIVE
pin.
DRIVE
pin.
DRIVE
/2. There is a potential
REF
Default /
Packaged
Setting
A
A
B
A
C
B
N/A
C
B
B