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¾
0~2
3
T1E
4
T1ON
5
T1S
6
T1M0
7
T1M1
Label
0
T2PSC0
1
T2PSC1
2
T2PSC2
3
T2E
4
T2ON
¾
5
6
T2M0
7
T2M1
Rev. 1.30
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enables/disables the timer counting (0=disable; 1=enable)
Defines the TMR1 internal clock source.
(0=f
/4; 1=32768Hz)
SYS
Defines the operating mode, T1M1, T1M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
Defines the prescaler stages, T2PSC2, T2PSC1, T2PSC0=
000: f
=f
INT
SYS
001: f
=f
/2
INT
010: f
=f
/4
INT
011: f
=f
/8
INT
100: f
=f
/16
INT
101: f
=f
/32
INT
SYS
110: f
=f
/64
INT
111: f
=f
/128
INT
SYS
Defines the TMR2 active edge of the timer/event counter:
In Event Counter Mode (T2M1,T2M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T2M1,T2M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enables/disables the timer counting (0=disable; 1=enable)
Unused bit, read as ²0²
Defines the operating mode, T2M1, T2M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR2C (2EH) Register
22
HT46RU67/HT46CU67
Function
June 10, 2014
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