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4.14.3.6
CPLD LED Control Register (CPLD_LEDS)
CPLD_LEDS controls the state of the CPLD's LEDs.
Address: 0x0800_0005 (CPLD_LEDS)
7
R
0
W
Reset:
0
Field
7–6
Reserved, must be cleared.
5–0
Controls the state of the CPLD's LED[5:0] signals. LED[5:0] corresponds to D35–D30.
CPLD_LED
0 Corresponding CPLD LED is OFF
1 Corresponding CPLD LED is ON
4.15
Interrupts
The four external MCF5445x interrupt requests are driven by the FPGA. The FPGA gathers four PCI
interrupts from the PCI slots, along with two pushbutton interrupts, and presents them to the MCF5445x.
Refer to
Section 4.13,
4.16
Serial Interface Header
The MCF5445x contains a few serial interfaces and timers that are not made available via dedicated
interfaces on the M54455EVB. However, these interfaces (and others) are brought out to a general purpose
header, J908, for easy access. The following interfaces are accessible on J908:
•
DSPI
2
•
I
C
•
DMA external request/acknowledge
•
DMA timer input/output
•
UART0
•
UART1
Table 34
shows the signal assignments on J908.
Freescale Semiconductor
6
5
0
0
0
Figure 24. CPLD_LEDS Register
Table 33. CPLD_LEDS Field Descriptions
"FPGA" for details on how to enable and route the interrupts.
M54455EVB User's Manual, Rev. 4
4
3
CPLD_LED
0
0
Description
2
1
0
0
0
0
33
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