Holtek HT46RU75D-1 Manual page 16

Power Down Operation - HALT
The Power-down mode is initialised by a ²HALT² instruc-
tion and results in the following.
·
The system oscillator turns off but the WDT oscillator
keeps running if the WDT oscillator or the real time clock
is selected.
·
The contents of the Data Memory and the registers re-
main unchanged.
·
The WDT is cleared and starts recounting if the WDT
clock is sourced from the WDT oscillator or the real time
clock oscillator.
·
All I/O ports maintain their original status.
·
The PDF flag is set but the TO flag is cleared.
·
The LCD driver keeps running if the WDT OSC or RTC
OSC is selected.
The system leaves the Power-down mode by means of an
external reset, an interrupt, an external falling edge signal
on port A, or by a WDT overflow. An external reset causes a
device initialisation, while a WDT overflow performs a
²warm reset². After examining the TO and PDF flags, the
reason for the device reset can be determined. The PDF
flag is cleared by a system power-up or by executing the
²CLR WDT² instruction, and is set by executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs, and
causes a wake-up that only resets the program counter and
the SP, and leaves the others in their original state.
A port A wake-up and interrupt methods can be considered
as a continuation of normal execution. Each pin of port A
can be independently selected to wake-up the device using
configuration options. After awakening from an I/O port
Bit No. Label
Specifies the LCD condition in the Power-down mode
0 LCDON 1: LCD module remains on (if OSCON=1) and ignores the configuration option setting
0: LCD condition decided by the LCD_ON configuration option
Defines the UART state when in the Power-down mode
1 UARTON 1: UART module remains on (if OSCON=1)
0: UART off
¾ Unused bit, read as ²0²
2~6
System clock oscillator On/off setting when in the Power-down mode
0: Oscillator stops running. All related peripherals will lose their clock and stop function-
7 OSCON ing. (Register bit 0 will be ignored)
1: Oscillator keeps running.
Rev. 1.10
(All peripheral keep running, except for the special setting of Bit 0)
HALTC (17H) Register
16
stimulus, the program will resume execution at the
next instruction. However, if awakening from an inter-
rupt, two sequences may occur. If the related inter-
rupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. But if the interrupt is enabled, and
the stack is not full, a regular interrupt response takes
place.
When an interrupt request flag is set before entering
the Power-down mode, the system cannot be awak-
ened using that interrupt.
If a wake-up events occur, it takes 1024 t
clock periods) to resume normal operation. In other
words, a dummy period is inserted after the wake-up.
If the wake-up results from an interrupt acknowledg-
ment, the actual interrupt subroutine execution is de-
layed by more than one cycle. However, if the
wake-up results in the next instruction execution, the
execution will be performed immediately after the
dummy period is finished.
To minimise power consumption, all the I/O pins
should be carefully managed before entering the
Power-down mode.
When a HALT instruction is executed, the CPU will
stop running, and the related OSC and peripheral
clocks will be set by the HALTC register. The HALTC
register will only take effect when the system clock
(f ) is set to OSC.
SYS
Note: HALTC has no effect if the 32K oscillator is
chosen as the system clock.
Function
HT46RU75D-1
(system
SYS
January 10, 2008