Holtek HT46RU75D-1 Manual page 11

low to high and high to low. Its related interrupt request
flag, EIF0; bit 4 of INTC0, must also be set. After the in-
terrupt is enabled, if the stack is not full and the external
interrupt is active, a subroutine call to location 04H oc-
curs. The interrupt request flag, EIF0, and EMI bits will
be cleared to disable other maskable interrupts.
The UART interrupt is initialised by setting the interrupt
request flag, which is the URF; bit 5 in the INTC0 regis-
ter. This is caused by a regular UART receive signal or a
a UART transmit signal. After the interrupt is enabled,
the stack is not full, and the URF bit is set, a subroutine
call to location 08H occurs. The related interrupt request
flag, URF, will be reset and the EMI bit will be cleared to
disable other interrupts.
The internal Timer/Event Counter 0 interrupt is gener-
ated when the Timer/Event Counter 0 interrupt request
flag is set, which is bit T0F; bit 6 of the INTC0 register.
This occurs when the timer overflows. After the interrupt
is enabled, if the stack is not full, and the T0F bit is set, a
subroutine call to location 0CH occurs. The related inter-
rupt request flag, T0F, will be reset, and the EMI bit will
be cleared to disable other maskable interrupts. The in-
terrupt for Timer/Event Counter 1 operates in a similar
manner but its related interrupt request flag is T1F,
which is bit 4 of INTC1, and its subroutine call location is
10H.
Bit No. Label
0 EMI Control the master (global) interrupt (1=enabled; 0=disabled)
1 EEI Control the external interrupt (1=enabled; 0=disabled)
2 EURI Controls the UART TX or RX interrupt (1/0: enable/disable)
3 ET0I Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
4 EIF0 External interrupt 0 request flag (1=active; 0=inactive)
5 URF UART TX or RX interrupt request flag (1=active; 0=inactive)
6 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
For test mode used only.
¾
7
Must be written as ²0²; otherwise may result in unpredictable operation.
Bit No. Label
0 ET1I Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
1 EADI Control the ADC interrupt (1=enabled; 0:disabled)
2 ERTI Control the real time clock interrupt (1=enabled; 0:disabled)
¾ Unused bit, read as ²0²
3, 7
4 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
5 ADF ADC request flag (1=active; 0=inactive)
6 RTF Real time clock request flag (1=active; 0=inactive)
Rev. 1.10
The A/D converter interrupt is generated when the A/D
converter interrupt request flag, ADF; bit 5 of INTC1 is
set. This occurs when an A/D conversion process has
completed. After the interrupt is enabled, if the stack is
not full, and the ADF bit is set, a subroutine call to loca-
tion 14H occurs. The related interrupt request flag, ADF,
is reset and the EMI bit is cleared to disable further
maskable interrupts.
The real time clock interrupt is generated when the real
time clock interrupt request flag, RTF; bit 6 of INTC1, is
set. After the interrupt is enabled, if the stack is not full,
and the RTF bit is set, a subroutine call to location 18H
occurs. The related interrupt request flag, RTF, is reset
and the EMI bit is cleared to disable further maskable in-
terrupts.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI² instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine, a
²RET² or ²RETI² instruction should be executed. A RETI
instruction sets the EMI bit and enables an interrupt ser-
vice, but a RET instruction does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
Function
INTC0 (0BH) Register
Function
INTC1 (1EH) Register
11
HT46RU75D-1
January 10, 2008