Analog Devices AD9396 Manual page 8

AD9396
Pin Type
OUTPUTS
REFERENCES
POWER SUPPLY
CONTROL
HDCP
DIGITAL VIDEO DATA
DIGITAL VIDEO CLOCK
INPUTS
DATA ENABLE
RTERM
Table 6. Pin Function Descriptions
Mnemonic Description
INPUTS
R Analog Input for the Red Channel 0.
AIN0
G Analog Input for the Green Channel 0.
AIN0
B Analog Input for the Blue Channel 0.
AIN0
B
R Analog Input for the Red Channel 1.
AIN1
G Analog Input for the Green Channel 1.
AIN1
B Analog Input for Blue Channel 1.
AIN1
B
High impedance inputs that accept the red, green, and blue channel graphics signals, respectively. The three channels
are identical and can be used for any colors, but colors are assigned for convenient reference. They accommodate input
signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation
(see Figure 3 for an input reference circuit).
Rx0+ Digital Input Channel 0 True.
Rx0− Digital Input Channel 0 Complement.
Rx1+ Digital Input Channel 1 True.
Rx1− Digital Input Channel 1 Complement.
Rx2+ Digital Input Channel 2 True.
Rx2− Digital input Channel 2 Complement.
These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel rate)
from a digital graphics transmitter.
Pin No. Mnemonic
89 DATACK
87 HSOUT
85 VSOUT
86 SOGOUT
84 O/E FIELD
24, 25, 26, 27 CTL(3-0)
57 FILT
80, 76, 72, V
D
67, 45, 33
100, 90, 10 V
DD
59, 56, 54 PV
DD
48, 32, 30 DV
DD
GND
83 SDA
82 SCL
49 DDCSCL
50 DDCSDA
51 MCL
52 MDA
35 Rx0+
34 Rx0−
38 Rx1+
37 Rx1−
41 Rx2+
40 Rx2−
43 RxC+
44 RxC−
88 DE
46 RTERM
Function
Data Output Clock
HSYNC Output Clock (Phase-Aligned with DATACK)
VSYNC Output Clock (Phase-Aligned with DATACK)
SOG Slicer Output
Odd/Even Field Output
Control 3, 2, 1, and 0.
Connection for External Filter Components for PLL
Analog Power Supply and DVI Terminators
Output Power Supply
PLL Power Supply
Digital Logic Power Supply
Ground
Serial Port Data I/O
Serial Port Data Clock
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
HDCP Master Serial Port Data Clock
HDCP Master Serial Port Data I/O
Digital Input Channel 0 True
Digital Input Channel 0 Complement
Digital Input Channel 1 True
Digital Input Channel 1 Complement
Digital Input Channel 2 True
Digital Input Channel 2 Complement
Digital Data Clock True
Digital Data Clock Complement
Data Enable
Sets Internal Termination Resistance
Rev. 0 | Page 8 of 48
Value
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
3.3 V
1.8 V to 3.3 V
1.8 V
1.8 V
0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
3.3 V CMOS
500 Ω