Analog Devices AD9396 Manual page 25

Hex Read/Write
Address or Read Only
0x26 Read/Write
0x27 Read/Write
0x28 Read/Write
0x29 Read/Write
0x2A Read/Write
0x2B Read/Write
0x2C Read/Write
0x2D Read/Write
0x2E Read/Write
0x2F Read
Default
Bits Value Register Name
[3:2] ****00** Output Mode
[1] ******1* Primary Output
Enable
[0] *******0
Secondary
Output Enable
[7] 0******* Output Three-
State
[6] *0****** SOG Three-State
[3] ****1*** Power-Down Pin
Polarity
[2:1] *****00* Power-Down Pin
Function
[0] *******0 Power-Down
[7] 1******* Auto Power-
Down Enable
[6] *0****** HDCP A0
[4] ***0**** BT656 EN
[3] ****0*** Force DE
Generation
[2:0] *****000 Interlace Offset
[7:2] 011000** VS Delay
[1:0] ******01 HS Delay MSB
[7:0] 00000100 HS Delay
[3:0] ****0101 Line Width MSB
[7:0] 00000000 Line Width
[3:0] ****0010 Screen Height
MSB
[7:0] 11010000 Screen Height
[7] 0******* Test 1
[6] *0****** TMDS Sync
Detect
[5] **0***** TMDS Active
[3] ****0*** HDCP Keys Read
[2:0] *****000 DVI Quality
Description
Selects which pins the data comes out on.
00 = 4:4:4 mode (normal).
01 = 4:2:2 + DDR 4:2:2 on blue.
10 = DDR 4:4:4 + DDR 4:2:2 on blue.
Enables primary output.
Enables secondary output (DDR 4:2:2 in Output Mode 1 and
Mode 2).
Three-states the outputs.
Three-states the SOG output.
Sets polarity of power-down pin.
0 = active low.
1 = active high.
Selects the function of the power-down pin.
00 = power-down.
01 = power-down and three-state SOG.
10 = three-state outputs only.
11 = three-state outputs and SOG.
0 = normal.
1 = power-down.
0 = disable auto low power state.
1 = enable auto low power state.
Sets the LSB of the address of the HDCP I
second receiver in a dual-link configuration.
0 = use internally generated MCLK.
1 = use external MCLK input.
Enables EAV/SAV codes to be inserted into the video output data.
Allows use of the internal DE generator in DVI mode.
Sets the difference (in HSYNCs) in field length between Field 0 and
Field 1.
Sets the delay (in lines) from VSYNC leading edge to the start of
active video.
MSB, Register 0x29.
Sets the delay (in pixels) from HSYNC leading edge to the start of
active video.
MSB, Register 0x2B.
Sets the width of the active video line (in pixels).
MSB, Register 0x2D.
Sets the height of the active screen (in lines).
Must be written to 1 for proper operation.
Detects a TMDS DE.
Detects a TMDS clock.
Returns 1 when read of EEPROM keys is successful.
Returns quality number based on DE edges.
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AD9396
2
C. Set to 1 only for a