Pin Configuration And Function Descriptions - Analog Devices AD9396 Manual

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND
GREEN 7
GREEN 6
GREEN 5
GREEN 4
GREEN 3
GREEN 2
GREEN 1
GREEN 0
V
DD
GND
BLUE 7
BLUE 6
BLUE 5
BLUE 4
BLUE 3
BLUE 2
BLUE 1
BLUE 0
NC
NC
NC
NC
CTL3
CTL2
NC = NO CONNECT
Table 5. Complete Pinout List
Pin Type
INPUTS
OUTPUTS
1
PIN 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin No. Mnemonic
79 R
AIN0
77 R
AIN1
74 G
AIN0
71 G
AIN1
68 B
AIN0
B
66 B
AIN1
B
64 HSYNC 0
63 HSYNC 1
61 VSYNC 0
60 VSYNC 1
73 SOGIN 0
70 SOGIN 1
62 EXTCLK
62 COAST
81 PWRDN
92 to 99 RED [7:0]
2 to 9 GREEN [7:0]
12 to 19 BLUE [7:0]
AD9396
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Function
Analog Input for Converter R Channel 0
Analog Input for Converter R Channel 1
Analog Input for Converter G Channel 0
Analog Input for Converter G Channel 1
Analog Input for Converter B Channel 0
Analog Input for Converter B Channel 1
Horizontal SYNC Input for Channel 0
Horizontal SYNC Input for Channel 1
Vertical SYNC Input for Channel 0
Vertical SYNC Input for Channel 1
Input for Sync-on-Green Channel 0
Input for Sync-on-Green Channel 1
External Clock Input—Shares Pin with COAST
PLL COAST Signal Input—Shares Pin with EXTCLK
Power-Down Control
Outputs of Red Converter, Bit 7 is MSB
Outputs of Green Converter, Bit 7 is MSB
Outputs of Blue Converter, Bit 7 is MSB
Rev. 0 | Page 7 of 48
AD9396
75 GND
74 G
AIN0
SOGIN 0
73
72 V
D
71 G
AIN1
70 SOGIN 1
69 GND
B
68
AIN0
V
67
D
B
66
AIN1
65 GND
64 HSYNC 0
HSYNC 1
63
62 EXTCLK/COAST
61 VSYNC 0
60 VSYNC 1
PV
59
DD
58 PGND
57 FILT
56 PV
DD
55 PGND
54 PV
DD
53 GND
52 MDA
51 MCL
Value
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
V
DD
V
DD
V
DD