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FEATURES
Analog/DVI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
150 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
DVI 1.0
150 MHz DVI receiver
Supports HDCP 1.1
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
GENERAL DESCRIPTION
The AD9396 offers designers the flexibility of an analog
interface and digital visual interface (DVI) receiver integrated
on a single chip. Also included is support for high bandwidth
digital content protection (HDCP).
The AD9396 is a complete 8-bit, 150 MSPS monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and 720p) and FPD resolutions up
to SXGA (1280 × 1024 @ 80 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), program-
mable gain, offset, and clamp control. The user provides only
1.8 V and 3.3 V power supply, analog input, and HSYNC.
Three-state CMOS outputs may be powered from 1.8 V to 3.3V.
The on-chip PLL generates a pixel clock from HSYNC. Pixel
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Dual-Display Interface
FUNCTIONAL BLOCK DIAGRAM
ANALOG INTERFACE
R/G/B OR YPbPr
IN0
2:1
CLAMP
MUX
R/G/B OR YPbPr
IN1
HSYNC 0
2:1
MUX
HSYNC 1
HSYNC 0
2:1
SYNC
MUX
HSYNC 1
PROCESSING
SOGIN 0
2:1
AND
MUX
SOGIN 1
CLOCK
GENERATION
COAST
FILT
CKINV
CKEXT
SCL
SERIAL REGISTER
SDA
AND
POWER MANAGEMENT
DIGITAL INTERFACE
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
DVI RECEIVER
Rx2–
RxC+
RxC–
RTERM
MCL
MDA
HDCP
DDCSCL
DDCSDA
clock output frequencies range from 12 MHz to 150 MHz. PLL
clock jitter is typically less than 700 ps p-p at 150 MHz. The
AD9396 also offers full sync processing for composite sync and
sync-on-green (SOG) applications.
The AD9396 contains a DVI-compatible receiver and supports
all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 80 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays may now receive
encrypted video content. The AD9396 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9396 is pro-
vided in a space-saving, 100-lead, surface-mount, Pb-free plastic
LQFP and is specified over the 0ºC to 70ºC temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
Analog/DVI
AD9396
R/G/B 8 × 3
A/D
OR YCbCr
2
DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REF
REFIN
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2
R/G/B 8 × 3
OR YCbCr
2
DATACK
DE
HSYNC
VSYNC
AD9396
Figure 1.
www.analog.com
DATACK
HSOUT
VSOUT
SOGOUT
DE
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Table of Contents
Related Manuals for Analog Devices AD9396
Summary of Contents for Analog Devices AD9396
-
Page 1: Features
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. -
Page 2: Table Of Contents
AD9396 TABLE OF CONTENTS Features ....................1 2-Wire Serial Register Map ............21 Applications..................1 2-Wire Serial Control Register Details ........29 Functional Block Diagram .............. 1 Chip Identification ..............29 General Description ................. 1 PLL Divider Control ..............29 Specifications.................. -
Page 3: Specifications
AD9396 SPECIFICATIONS ANALOG INTERFACE ELECTRICAL CHARACTERISTICS = 3.3 V, DV = PV = 1.8 V, ADC clock = maximum. Table 1. AD9396KSTZ-100 AD9396KSTZ-150 Parameter Temp Test Level Unit RESOLUTION Bits DC ACCURACY Differential Nonlinearity 25°C –0.6 +1.6/–1.0 ±0.7 +1.8/–1.0 Integral Nonlinearity 25°C... -
Page 4: Digital Interface Electrical Characteristics
AD9396 AD9396KSTZ-100 AD9396KSTZ-150 Parameter Temp Test Level Unit POWER SUPPLY Supply Voltage Full 3.15 3.47 3.15 3.47 Supply Voltage Full Supply Voltage Full 3.47 3.47 Supply Voltage Full Supply Current (V 25°C Supply Current (DV 25°C DVDD Supply Current (V 25°C... - Page 5 AD9396 AD9396KSTZ-100 AD9396KSTZ-150 Test Parameter Level Conditions Unit POWER SUPPLY Supply Voltage 3.15 3.47 3.15 3.47 Supply Voltage Supply Voltage Supply Voltage Supply Current (Typical Pattern) Supply Current (Typical Pattern) 1, 4 Supply Current (Typical Pattern) DVDD Supply Current (Typical Pattern)
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Page 6: Absolute Maximum Ratings
AD9396 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress 3.6 V rating only; functional operation of the device at these or any 3.6 V... -
Page 7: Pin Configuration And Function Descriptions
AD9396 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 GREEN 7 AIN0 GREEN 6 SOGIN 0 GREEN 5 GREEN 4 AIN1 GREEN 3 SOGIN 1 GREEN 2 GREEN 1 AIN0 GREEN 0 AD9396 AIN1 TOP VIEW (Not to Scale) BLUE 7... - Page 8 AD9396 Pin Type Pin No. Mnemonic Function Value OUTPUTS DATACK Data Output Clock HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) VSOUT VSYNC Output Clock (Phase-Aligned with DATACK) SOGOUT SOG Slicer Output O/E FIELD Odd/Even Field Output 24, 25, 26, 27 CTL(3-0) Control 3, 2, 1, and 0.
- Page 9 EXTCLK functionality. RTERM RTERM is the termination resistor used to drive the AD9396 internally to a precise 50 Ω termination for TMDS lines. This should be a 500 Ω 1% tolerance resistor.
- Page 10 Clock Generator Power Supply. The most sensitive portion of the AD9396 is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.
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Page 11: Design Guide
C) on the a sync signal directly from the graphics source, or a prepro- AD9396 operate to 3.3 V CMOS levels. In addition, all digital cessed TTL or CMOS level signal. inputs except the TMDS (HDMI/DVI) inputs are 5 V tolerant. - Page 12 Clamp timing employs the AD9396 internal clamp timing The offset on the AD9396 can be adjusted automatically to a generator. The clamp placement register is programmed with specified target code. This option allows the user to set the...
- Page 13 AD9396 clock generation circuit to minimize function is driven from the VSYNC signal, which is typically a jitter. The clock jitter of the AD9396 is less than 13% of the total time when HSYNC signals can be disrupted with extra pixel time in all operating modes, making the reduction in the equalization pulses.
- Page 14 AD9396 Power Management The AD9396 uses the activity detect circuits, the active interface by Register 0x26[3]) can drive the chip into four power-down bits in the serial bus, the active interface override bits, the options. Bit 2 and Bit 1 of Register 0x26 control these four power-down bit, and the power-down pin to determine the options.
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Page 15: Timing
The known output polarity can be programmed either active high or active low (Register 0x24, Bit 7). Second, There is a pipeline in the AD9396, which must be flushed HSOUT is aligned with DATACK and data outputs. Third, the before valid data becomes available. - Page 16 Sync Processing is to extract VSYNC from the composite sync signal, which can The inputs of the sync processing section of the AD9396 are come from either the sync slicer or the HSYNC input. The combinations of digital HSYNCs and VSYNCs, analog sync-on-...
- Page 17 200 ns multiplier value. The maximum varia- bility over all operating conditions is ±20% (160 ns to 240 ns). The sync separator on the AD9396 is simply an 8-bit digital Because normal VSYNC and HSYNC pulse widths differ by a counter with a 6 MHz clock.
- Page 18 AD9396 HSYNC Filter and Regenerator timing, program a value (x) into Register 0x20. The resulting The HSYNC filter is used to eliminate any extraneous pulses filter window time is ±x times 25 ns around the regenerated from the HSYNC or SOGIN inputs, outputting a clean, low HSYNC leading edge.
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Page 19: Dvi Receiver
HSYNC leading edges from switching at the same time, eliminating confusion as to when the first line of a frame The AD9396 contains a filter that allows it to convert a signal occurs. Enabling the VSYNC filter is done with Register from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the 0x21[5]. -
Page 20: Timing Diagrams
The following timing diagrams show the operation of the [11:0] × × 4096 AD9396.The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to Figure 13. Single CSC Channel DATAIN HSIN... -
Page 21: 2-Wire Serial Register Map
AD9396 2-WIRE SERIAL REGISTER MAP The AD9396 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 12. Control Register Map... - Page 22 AD9396 Read/Write Default Address or Read Only Bits Value Register Name Description 0x12 Read/Write 1******* Input HSYNC 0 = active low. Polarity 1 = active high. *0****** HSYNC Polarity 0 = auto HSYNC polarity. Override 1 = manual HSYNC polarity.
- Page 23 AD9396 Read/Write Default Address or Read Only Bits Value Register Name Description *******0 Bad Sync Detect 0 = not detected. 1 = detected. 0x17 Read [3:0] ****0000 HSYNCs per MSB of HSYNCs per VSYNC. VSYNC MSB 0x18 Read [7:0] 00000000 HSYNCs per HSYNCs per VSYNC count.
- Page 24 AD9396 Read/Write Default Address or Read Only Bits Value Register Name Description 0x21 Read/Write 1******* SP Sync Filter Enables coast, VSYNC duration, and VSYNC filter to use the Enable regenerated HSYNC rather than the raw HSYNC. *1****** PLL Sync Filter...
- Page 25 AD9396 Read/Write Default Address or Read Only Bits Value Register Name Description [3:2] ****00** Output Mode Selects which pins the data comes out on. 00 = 4:4:4 mode (normal). 01 = 4:2:2 + DDR 4:2:2 on blue. 10 = DDR 4:4:4 + DDR 4:2:2 on blue.
- Page 26 AD9396 Read/Write Default Address or Read Only Bits Value Register Name Description 0x30 Read *0****** DVI Content This bit is high when HDCP decryption is in use (content is Encrypted protected). The signal goes low when HDCP is not being used.
- Page 27 AD9396 Read/Write Default Address or Read Only Bits Value Register Name Description 0x39 Read/Write [4:0] ***00000 CSC_Coeff_A3 MSB, Register 0x3A. 0x3A Read/Write [7:0] 00000000 CSC_Coeff_A3 LSB CSC coefficient for equation: = (A1 × R ) + (A2 × G ) + (A3 × B ) + A4 = (B1 ×...
- Page 28 AD9396 Read/Write Default Address or Read Only Bits Value Register Name Description 0x4B Read/Write [4:0] ***11000 CSC_Coeff_C4 MSB, Register 0x4C. 0x4C Read/Write [7:0] 10111101 CSC_Coeff_C4 CSC coefficient for equation: = (A1 × R ) + (A2 × G ) + (A3 × B ) + A4 = (B1 ×...
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Page 29: 2-Wire Serial Control Register Details
0x69, PLLDIVL = 0xDx). Bit[2] External Clock Enable The AD9396 updates the full divide ratio only when the LSBs This bit determines the source of the pixel clock. are changed. Writing to this register by itself does not trigger an A Logic 0 enables the internal PLL that generates the pixel clock update. -
Page 30: Input Gain
These eight bits are the green channel offset control. The offset control shifts the analog input, resulting in a change in bright- These bits control the PGA of the green channel. The AD9396 ness. Note that the function of the offset register depends on can accommodate input signals with a full-scale range of whether clamp feedback is enabled (Register 0x1C, Bit 7 = 1). -
Page 31: Coast And Clamp Controls
AD9396 0x10—Bits[7:2] SOG Comparator Threshold Exit 0x12—Bit[4] VSYNC Polarity Override The exit level for the SOG slicer. Must be > the enter level 0 = auto VSYNC polarity, 1 = manual VSYNC polarity. Manual (Register 0x0F). The power-up default is 0x10. -
Page 32: Polarity Status
AD9396 0x15—Bit[5] VSYNC0 Detection Bit 0x16—Bit[2] Pseudo Sync Detected 0x16—Bit[1] Sync Filter Locked Indicates if VSYNC0 is active. This bit is used to indicate when activity is detected on the VSYNC0 input pin. If VSYNC is held Indicates whether sync filter is locked to periodic sync signals. - Page 33 AD9396 0x1B—Bit[3] Clamp Disable 0x1F—Bits[7:0] Sync Filter Unlock Threshold 0 = internal clamp enabled. 1 = internal clamp disabled. The This 8-bit register is programmed to set the number of missing power-up default is 0. or invalid HSYNCs needed to unlock the sync filter. This disables the filter operation when there is no longer a stable 0x1B —Bits[2:1] Programmable Bandwidth...
- Page 34 PLL feedback clock. normal pixel clock. The power-up default setting is 01. The AD9396 then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Table 16. Output Clock Select HSYNC output, which is also phase-adjusted.
- Page 35 AD9396 0x26—Bit[6] SOG Three-State 0x25—Bits[5:4] Output Drive Strength When enabled, this bit allows the SOGOUT pin to be placed in These two bits select the drive strength for all the high speed a high impedance state. 0 = normal SOG output. 1 = SOGOUT digital outputs (except VSOUT, A0, and the O/E Field).
-
Page 36: Bt656 Generation
AD9396 BT656 GENERATION 0x2F—Bit[4] AV Mute 0x27—Bit[4] BT656 Enable This read-only bit indicates the presence of AV mute based on general control packets. 0 = AV not muted. 1 = AV muted. This bit enables the output to be BT656-compatible with defined start of active video (SAV) and end of active video 0x2F—Bit[3] HDCP Keys Read... -
Page 37: Color Space Conversion
AD9396 0x35—Bits[4:0] Color Space Conversion Coefficient 0x33—Bit[6] Macrovision Settings Override A1 MSBs This defines whether preset values are used for the MV line These 5 bits form the 5 MSBs of the Color space Conversion counts and pulse widths or the values stored in I C registers. - Page 38 AD9396 0x44—Bits[7:0] CSC B4 LSBs 0x59—Bit[5] CLK Term O/R 0x45—Bits[4:0] CSC C1 MSBs This bit allows for overriding during power down. 0 = auto, 1 = manual. The default value for the 13-bit C1 is 0x0000. 0x59—Bit[4] Manual CLK Term 0x46—Bits[7:0 CSC C1 LSBs...
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Page 39: 2-Wire Serial Control Port
Data Transfer via Serial Interface A 2-wire serial interface control is provided in the AD9396. Up to two AD9396 devices can be connected to the 2-wire serial For each byte of data read or written, the MSB is the first bit of interface, with a unique address for each device. - Page 40 AD9396 Serial Interface Read/Write Examples Write to one control register: Read from one control register: • • Start signal Start signal • • Slave address byte (R/ W bit = low) Slave address byte (R/ W bit = low) •...
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Page 41: Pcb Layout Recommendations
AD9396 PCB LAYOUT RECOMMENDATIONS The AD9396 is a high precision, high speed analog device. To The bypass capacitors should be physically located between the achieve the maximum performance from the part, it is impor- power plane and the power pin. Current should flow from the tant to have a well laid-out board. -
Page 42: Outputs (Both Data And Clocks)
EMI, and reduce the current spikes inside of the AD9396. If series resistors are used, place them as close as possible to the AD9396 pins (although try not to add vias or extra length to the output trace to move the resistors closer). -
Page 43: Color Space Converter (Csc) Common Settings
AD9396 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 22. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9396) Register Red/Cr Coeff 1 Red/Cr Coeff 2 Red/Cr Coeff 3 Red/Cr Offset Address 0x35 0x36 0x37 0x38... - Page 44 AD9396 Table 26. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Red/Cr Coeff 2 Red/Cr Coeff 3 Red/Cr Offset Address 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C Value 0x28 0x2D 0x18 0x93 0x1F...
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Page 45: Outline Dimensions
AD9396 OUTLINE DIMENSIONS 16.00 1.60 MAX BSC SQ 0.75 0.60 0.45 PIN 1 14.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 0.15 0° SEATING 0.05 0.08 MAX PLANE 0.27 COPLANARITY VIEW A 0.22 0.50 VIEW A 0.17... - Page 46 AD9396 NOTES Rev. 0 | Page 46 of 48...
- Page 47 AD9396 NOTES Rev. 0 | Page 47 of 48...
- Page 48 AD9396 NOTES Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
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