Lauterbach TRACE32-ICD Manual

Lauterbach TRACE32-ICD Manual

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PPC600 Family Debugger

Release 02.2022
MANUAL

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  • Page 1: Ppc600 Family Debugger

    PPC600 Family Debugger Release 02.2022 MANUAL...
  • Page 2: Table Of Contents

    Software Breakpoints in Interrupt Handlers Breakpoints in FLASH/ROM Breakpoints on Physical or Virtual Addresses Examples for Breakpoints Software Breakpoints On-chip Program Address Breakpoints On-chip Data Address Breakpoints Access Classes Access Classes to Memory and Memory Mapped Resources 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 3 SYStem.Option.MMUSPACES Separate address spaces by space IDs SYStem.Option.NoDebugStop Disable JTAG stop on debug events SYStem.Option.NOTRAP Use alternative software breakpoint instruction SYStem.Option.OVERLAY Enable overlay support SYStem.Option.PARITY Generate parity on memory access SYStem.Option.PINTDebug Program interrupt debugging 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 4 TrOnchip.TOFF Switch the sampling to the trace to OFF TrOnchip.TON Switch the sampling to the trace to “ON” TrOnchip.TTrigger Set a trigger for the trace Mechanical Description ....................JTAG/COP Connector PPC603e/700/MPC8200 Technical Data ........................1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 5 PPC600 Family Debugger Version 09-Mar-2022 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 6: Introduction

    (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.
  • Page 7: Warning

    Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the Debug Cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 8: Target Design Requirement/Recommendations

    VCCS = 1. 8V Blue ribbon The VCCS pin should be connected to VCC through a resistor with max. 10 , as the output buffers are directly supplied by the VCCS pin. cable 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 9: Quick Start

    Load the program and debug symbols. Data.LOAD.Elf diabc.x If the program was compiled on a different computer / environment, the source file path might have to be adopted. Data.LOAD.Elf diabc.x /StripPART 5. /SOURCEPATH "L:\prj\src" 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 10 Start application. The core will halt when the breakpoint is reached. Open windows to show source code, core registers and local variables. The window position can be specified with the WinPOS command. Data.List Register.view /SpotLight Frame.view /Locals /Caller 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 11: Troubleshooting

    If the target reset is asserted for >500ms, or the target reset state is not reflected on the JTAG_HReset pin, SYStem.Option.SLOWRESET target reset fail might be necessary. emulator debug port reset error 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 12: Problems With Memory Access

    Always set the right base address with SYStem.Option.BASE before opening the peripheral view. • Protect the debugger from accessing unimplemented memory using MAP.DENYACCESS. Please refer to our Frequently Asked Questions page on the Lauterbach website. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 13: Configuration

    1 GBit Ethernet Target Debug Cable POWER DEBUG PRO Ethernet Cable POWER DEBUG PRO PC or Workstation Target Debug Cable POWER DEBUG USB INTERFACE / USB 3 Cable POWER DEBUG INTERFACE / USB 3 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 14: Powerpc 600 Family Specific Implementations

    Since this CPU can only be stopped by an on-chip breakpoint, TRACE32-ICD sets an on-chip breakpoint to the Trap exception handler, whenever a software breakpoint is used. Because of that, software breakpoints can not be used if all on-chip breakpoints are directly used.
  • Page 15: Software Breakpoint Handling

    Break error! Manual-Mode 0/1 Command Sequence / CPU Status MSR[IP] Exception Pos Comment CPU is stopped, PC at 0x00 CPU stop at 0x08 Break OK. set sys.option.ip 0 CPU stop at 0x1C Break OK. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 16 Software breakpoints can be overwritten by the target application, e.g. if a breakpoint is set in an area which will be loaded by a boot loader. Use on-chip breakpoints in this case. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 17: On-Chip Breakpoints

    On-chip Breakpoints The following list gives an overview of the usage of the on-chip breakpoints by TRACE32-ICD: • CPU family • Instruction breakpoints: Number of on-chip breakpoints that can be used for program and spot breakpoints • Read/Write breakpoints: Number of on-chip breakpoints that can be used as read or write breakpoints.
  • Page 18: Software Breakpoints In Interrupt Handlers

    This command will enable MMU support, including breakpoint configuration. Software breakpoints hit on virtual addresses if MSR_IR is set, and on physical addresses if MSR_IR is not set, regardless of any other configuration. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 19: Examples For Breakpoints

    ; single address write Break.Set 0xFFF00244 /readwrite ; single address any Break.Set nMyValue /write ; variable name Break.Set 0x2000--0x2fff /readwrite ; address range Data address breakpoints of all PPC603e based cores will operate on 8 byte boundaries. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 20: Access Classes

    In addition to the access classes, there are access class attributes: Examples: Command: Effect: Data.List SP:0x1000 Opens a List window displaying supervisor program memory Data.Set ED:0x3330 0x4F Write 0x4F to address 0x3330 using real-time memory access 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 21: Access Classes To Other Addressable Core And Peripheral Resources

    (*) updated updated 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 22: Mesi States

    CPU as the flags Valid and Dirty. The debugger will display both MESI state and the status flag representation. State translation table: MESI state Flag M (modified) Valid && Dirty E (exclusive) Valid && NOT Dirty S (shared) Shared I (invalid) NOT Valid 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 23: Little Endian Operation

    MPC5123 MPC5125 MGT5100 HID2[TLE] == 1 for true little endian MPC5200 MPC74XX — MPC8247 — MPC8248 MPC8271 MPC8272 MPC83XX — e300 core only supports true little endian MPC86XX — 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 24: Cpu Specific System Commands

    CPUs that appeared later than the software release are usually not supported. Please check www.lauterbach.com for updates. If the needed CPU appeared after the release date of the debugger software, please contact technical support and request a software update.
  • Page 25: System.lock

    E:0x100) or by using the format option %E (e.g. Var.View %E var1). It is also possible to activate this non-intrusive memory access for all memory ranges displayed on the TRACE32 screen by setting SYStem.Option.DUALPORT NOTE: SYStem.MemAccess Enable is only available for the MPC86XX. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 26: System.mode

    Resets the target and sets the CPU to debug mode. After execution of this command the CPU is stopped and prepared for debugging. All register are set to the default value. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 27: System.config.state

    Informs the debugger about the position of the Test Access Ports (TAP) in the JTAG chain which the debugger needs to talk to in order to access the debug and trace facilities on the chip. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 28: System.config

    Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down resistor, other trigger inputs need to be kept in inactive state. Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701). 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 29 (default: 7 = Select-DR-Scan) This is the state of the TAP controller when the debugger switches to tristate mode. All states of the JTAG TAP controller are selectable. TCKLevel (default: 0) Level of TCK signal when all debuggers are tristated. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 30 (default: OFF) If more than one debugger share the same debug port, all except one must have this option active. JTAG: Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 31: Daisy-Chain Example

    SYStem.CONFIG.IRPOST 8. ; IR Core A + B SYStem.CONFIG.DRPRE ; DR Core D SYStem.CONFIG.DRPOST 2. ; DR Core A + B SYStem.CONFIG.CORE 0. 1. ; Target Core C is Core 0 in Chip 1 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 32: Tapstates

    Exit1-IR Shift-IR Pause-IR Run-Test/Idle Update-IR Capture-IR Test-Logic-Reset SYStem.CONFIG.CHKSTPIN Control pin 8 of debug connector Format: SYStem.CONFIG.CHKSTPIN LOW | HIIGH Default: HIGH. Controls the level of pin 8 (/CHKSTP_IN or /PRESENT) of the debug connector. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 33: System.config.core Assign Core To Trace32 Instance

    GUI uses a new chip_index according to its CORE= parameter of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must be merged by calling SYStem.CONFIG.CORE. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 34: System.config.driverstrength

    Controls the level and function of pin 2 (/QACK) of the debug connector. Default: TRISTATE. TRISTATE Pin is disabled (tristate). QREQ Pin is driven to level of QREQ (pin 5). Pin is driven to GND permanently. HIGH Pin is driven to JTAG_VREF permanently. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 35: Cpu Specific System Commands

    The debugger will determine the current base address via JTAG access. This option has no effect. PPC603x, PPC750xx, MPC755, PPC74XX SYStem.Option.BASE is usually not required. It can be used to set the base address of the memory mapped registers of an external memory/peripheral controller (MPC10X, TSI1xx, MV6xxxx, etc.) 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 36: System.option.bus32

    AUTO, this setting defines if the RCW is read from the location designated to the configuration master, or from one of the seven locations designated to the configuration slaves. By default setting, the debugger will read from the configuration master location. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 37: System.option.dcread

    Please note that while the CPU is running, MMU address translation can not be accesses by the debugger. Only physical addresses accesses are possible. Use the access class modifier “A:” to declare the access physical addressed, or declare the address translation in the debugger-based MMU manually using TRANSlation.Create. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 38: System.option.freeze Freeze Timebase When Core Halted

    SYStem.Option.FREEZE Freeze timebase when core halted Format: SYStem.Option.FREEZE [ON | OFF] When enabled, the core’s timebase is stopped when the core is halted in debug mode. It is recommended to set this option ON. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 39: System.option.holdreset

    The command defines the hook address. After program break the hook address is compared against the program counter value. If the values are equal, it is supposed that a hook function was executed. This information is used to determine the right break address by the debugger. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 40: System.option.hrcwoverride

    SYStem.Option.ICFLUSH [ON | OFF] Invalidates the instruction cache before starting the target program (Step or Go). Write accesses by the debugger to the memory of the class P: are performed in the instruction cache and the memory. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 41: System.option.icread

    NOTE: Don’t enable this option for code that disables MSR_EE. The debugger will disable MSR_EE while the CPU is running and restore it after the CPU stopped. If a part of the application is executed that disables MSE_EE, the debugger can not detect this change and will restore MSE_EE. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 42: System.option.ip

    Format: SYStem.Option.MemProtect [ON | OFF] PowerQuicc II (MPC824X, MPC826X, MPC827X, MPC8280) only. This option can help to prevent a hanging memory bus caused by debugger accesses to unimplemented memory. USe together with SYStem.Option.BASE AUTO. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 43: System.option.memspeed

    1 (fastest) … 255 (slowest) 0 (default speed) This option can be used to configure the access speed for memory accesses by the debugger. Only use this option when advised by Lauterbach. SYStem.Option.MMUSPACES Separate address spaces by space IDs Format: SYStem.Option.MMUSPACES [ON | OFF]...
  • Page 44: System.option.nodebugstop

    Enable this option if the CPU should not stop for JTAG on debug events, in order to allow a target application to use debug events. Typical usages for this option are run-mode debugging (e.g. with gdbserver) or setting up the system for a branch trace via LOGGER (trace data in target RAM) or INTEGRATOR. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 45: System.option.notrap

    JTAG. Illegal instructions as software breakpoints will preserve SRR0/1 registers. If the program interrupt is required by the application, and both FPU and ILL are not usable, use SYStem.Option.PINTDebug as workaround. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 46: System.option.overlay

    Example: SYStem.Option.OVERLAY ON Data.List 0x2:0x11c4 ; Data.List <overlay_id>:<address> SYStem.Option.PARITY Generate parity on memory access Format: SYStem.Option.PARITY [ON | OFF] Compute the parity bit for the Data.Set command to support memory with parity. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 47: System.option.pintdebug

    Enable this system option if the PowerPC core is operated in modified (PowerPC) little endian mode. If the CPU is configured for true little endian mode, use the command SYStem.Option.LittleEnd. To find out which mode is supported by the target processor, see Little Endian Operation. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 48: System.option.pte

    No actions to the processor take place when a reset is detected. Information about the reset will be printed to the message AREA. AsyncHalt Halt core as soon as possible after reset was detected. The core will halt shortly after the reset event. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 49: System.option.resetmode

    HRESET can be determined via JTAG_HRESET. If this system option is enabled, the debugger will not read JTAG_HRESET, but instead waits four seconds and then assumes that the boards HRESET is released. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 50: System.option.stepsoft

    In this case, declare the read-only memory using MAP.BOnchip, and the RAM used by the debugger using FLASH.TARGET. NOTE: The alternative workaround can only fix issues caused by single steps. Manual breaks and on-chip breakpoints can still be affected by the problem. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 51: System.option.waitreset

    A wait time of several ms should be sufficient. If a wait time > 10ms is required, the target might require a stronger RESET pull-up resistor. hold time wait time RESET pin RESET/BIST RESET DEBUG_HALT CPU State 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 52: System.option.watchdog

    The SWT can be disabled or its time-out period can be changed in the SYPCR. Once the SYPCR is written, it cannot be written again until a system reset. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 53: Cpu Specific Mmu Commands

    Displays the entries of an MMU translation table. • if <range> or <address> have a space ID: displays the translation table of the specified process • else, this command displays the table the CPU currently uses for MMU translation. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 54 This command reads the table of the specified process, <space_id>:0x0 and displays its table entries. • For information about the first three parameters, see “What to know about the Task Parameters” (general_ref_t.pdf). • See also the appropriate OS Awareness Manuals. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 55: Mmu.list

    Lists the entries of an MMU translation table. • if <range> or <address> have a space ID: list the translation table of the specified process • else, this command lists the table the CPU currently uses for MMU translation. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 56 This command reads the table of the specified process, <space_id>:0x0 and lists its address translation. • For information about the first three parameters, see “What to know about the Task Parameters” (general_ref_t.pdf). • See also the appropriate OS Awareness Manuals. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 57: Mmu.scan

    This command reads the OS kernel MMU table and the MMU tables of all processes and copies the complete address translation into the debugger- internal static translation table. See also the appropriate OS Awareness Manual. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 58: Mmu.set

    Index (entry/set number) in TLB table <tlbhi>, <tlblo>, Data of the TLB entry. <tlbext> <way> Way number within the set DTLB Translation lookaside buffer for data load and store accesses ITLB Translation lookaside buffer for instruction fetches 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 59: Cpu Specific Benchmarkcounter Commands

    The table below explains the meaning of the individual states. <state> Dependency in core USER Counter frozen if MSR[PR]==1 SUPERVISOR Counter frozen if MSR[PR]==0 MASKSET Counter frozen if MSR[PMM]==1 MASKCLEAR Counter frozen if MSR[PMM]==0 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 60: Bmc.freeze Freeze Counters While Core Halted

    Enable this setting to prevent that actions of the debugger have influence on the performance counter. As this feature software controlled (no on-chip feature), some events (especially clock cycle measurements) may be counted inaccurate even if this setting is set ON. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 61: Cpu Specific Tronchip Commands

    CPU specific TrOnchip Commands The features supported by the TrOnchip command for TRACE32-ICD vary for the different PowerPC families. TrOnchip.DISable Disable debug register control Format: TrOnchip.DISable Not supported. The debugger always controls the debug registers. TrOnchip.ENable Enable debug register control Format: TrOnchip.ENable...
  • Page 62: Tronchip.varconvert

    Resets the trigger system to the default state. TrOnchip.state Display on-chip trigger window Format: TrOnchip.state Opens the TrOnchip.state window. TrOnchip.TEnable Set filter for the trace Format: TrOnchip.TEnable <par> (deprecated) Refer to the Break.Set command to set trace filters. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 63: Tronchip.toff

    TrOnchip.TON EXT | Break (deprecated) Refer to the Break.Set command to set trace filters. TrOnchip.TTrigger Set a trigger for the trace Format: TrOnchip.TTrigger <par> (deprecated) Refer to the Break.Set command to set a trigger for the trace. 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 64: Mechanical Description

    Signal in brackets are not needed by the debugger and can be left uncon- nected. • If CPUs have an QACK input and this input is unused, QACK should be connected to GND. If the processor does not have QACK/QREQ pins, leave pin 2 and 15 N/C 1989-2022 © Lauterbach PPC600 Family Debugger...
  • Page 65: Technical Data

    Technical Data 1989-2022 © Lauterbach PPC600 Family Debugger...

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