(the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.
Since this CPU can only be stopped by an on-chip breakpoint, TRACE32-ICD sets an on-chip breakpoint to the Trap exception handler, whenever a software breakpoint is used. Because of that, software breakpoints can not be used if all on-chip breakpoints are directly used.
On-chip Breakpoints The following list gives an overview of the usage of the on-chip breakpoints by TRACE32-ICD: • CPU family • Instruction breakpoints: Number of on-chip breakpoints that can be used for program and spot breakpoints • Read/Write breakpoints: Number of on-chip breakpoints that can be used as read or write breakpoints.
CPUs that appeared later than the software release are usually not supported. Please check www.lauterbach.com for updates. If the needed CPU appeared after the release date of the debugger software, please contact technical support and request a software update.
1 (fastest) … 255 (slowest) 0 (default speed) This option can be used to configure the access speed for memory accesses by the debugger. Only use this option when advised by Lauterbach. SYStem.Option.MMUSPACES Separate address spaces by space IDs Format: SYStem.Option.MMUSPACES [ON | OFF]...
CPU specific TrOnchip Commands The features supported by the TrOnchip command for TRACE32-ICD vary for the different PowerPC families. TrOnchip.DISable Disable debug register control Format: TrOnchip.DISable Not supported. The debugger always controls the debug registers. TrOnchip.ENable Enable debug register control Format: TrOnchip.ENable...
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