Xycom XVME-113 User Manual page 56

Appendix A - VMEbus Connector/Pin Description
Signal
Mnemonic
IACK*
IRQ1*
IRQ7*
LWORD*
(RESERVED)
SERCLK
SERDAT
SYSCLK
A-4
Table A-1. VMEbus Signal Identification (Continued)
Connector
and
Pin Number
1A:20 INTERRUPT ACKNOWLEDGE: Open-collector or three-state driven
signal from any master processing an interrupt request. It is routed via
the backplane to slot 1, where it is looped-back to become slot 1
IACKIN* in order to start the interrupt acknowledge daisy-chain.
INTERRUPT REQUEST (1-7): Open-collector driven signals,
generated by an interrupter, which carry prioritized interrupt requests.
1B:24-30 Level seven is the highest priority.
LONGWORD: Three-state driven signal indicates that the current
transfer is a 32-bit transfer.
1C:13 RESERVED: Signal line reserved for future VMEbus enhancements.
This line must not be used.
2B:3 A reserved signal which will be used as the clock for a serial
communication bus protocol which is still being finalized.
1B:21 A reserved signal which will be used as a transmission line for serial
communication bus messages.
SYSTEM CLOCK: A constant 16-MHz clock signal that is
1B:22 independent of processor speed or timing. It is used for general system
timing use.
1A:10
Signal Name and Description